Module 1.3 - Decoupling & Bypass
Ensuring clean, stable power delivery to every IC through proper capacitor strategy
Ensuring clean, stable power delivery to every IC through proper capacitor strategy
Local decoupling means placing a capacitor (typically 100nF ceramic) as physically close as possible to each IC's power pin(s). This capacitor serves as a local energy reservoir, supplying instantaneous current during switching transitions before the power plane can respond. The capacitor must be placed between the VCC pin and the nearest GND pin of the same IC.
This is perhaps the single most critical passive component placement decision in any digital design.
When a digital IC switches (every clock edge), it draws transient current spikes of nanosecond duration. The inductance of even 1cm of PCB trace prevents the power supply from responding fast enough. Without local decoupling, the IC's power pin voltage drops (ground bounce) causing logic errors, increased EMI radiation, and reduced noise margins. A missing 100nF cap can cause intermittent failures that are extremely difficult to diagnose.
STM32F407 decoupling (per ST datasheet AN4488):
VDD pins (x4): Each gets 100nF X7R 0402 + shared 4.7uF X5R 0805 VDDA (analog): 1uF + 100nF in series with ferrite bead from VDD VREF+: 1uF + 100nF (separate from VDDA for noise isolation) VBAT: 100nF (for RTC backup) VCAP1, VCAP2: 2.2uF each (internal regulator output - NOT decoupling, but required)
IC with no decoupling: 74HC595 shift register has VCC (pin 16) and GND (pin 8) but no capacitor between them on the schematic. The nearest decoupling cap is 3 inches away on another IC's power pin. At 10MHz clock rate, the 595 generates 50mV switching noise on VCC, causing random bit errors on the serial data output that appear once every ~10,000 shifts.
KiCad: Use ERC to find power pins without nearby passive connections. Visually verify each IC has associated caps in the schematic. In PCB editor, use DRC to check cap-to-IC distances.
Altium: Create a design rule for maximum distance between decoupling cap and IC power pin. Use ActiveBOM to cross-reference IC count vs. decoupling cap count.
OrCAD: Use part-level properties to link decoupling capacitors to their parent IC. Run cross-reference report to verify every IC has associated caps.
Bulk capacitors (10uF - 1000uF) provide energy storage for medium-frequency transients (kHz to low MHz range) and current surges that local 100nF caps cannot sustain. They bridge the gap between the power supply's response time (microseconds) and the local decoupling's capacity. Bulk caps are placed near power supply outputs and near major current-drawing ICs (MCUs, FPGAs, power amplifiers).
The power delivery network forms a hierarchy: regulator output cap -> bulk caps -> local decoupling caps.
Without adequate bulk capacitance, power rail voltage droops when a large transient load activates (e.g., radio transmitter keying on, motor starting, LED array switching). The regulator needs time to respond and increase current output - the bulk cap supplies energy during this response time. Insufficient bulk capacitance causes voltage dips that can reset MCUs, corrupt flash write operations, or cause communication errors.
TPS62130 output capacitor network:
Output (3.3V rail): - 2x 22uF X5R 0805 ceramic (right at regulator output - required for stability) - 47uF polymer electrolytic (near MCU cluster for sustained current delivery) - Individual 100nF local caps at each IC Total output capacitance: 91uF (44uF ceramic + 47uF polymer) ESR range: 2-10 mOhm (meets TPS62130 stability requirement of < 50 mOhm)
Minimal output cap: TPS62130 regulator with only a single 10uF 0402 ceramic at the output (actual capacitance at 3.3V bias: ~5uF due to DC bias effect). No additional bulk capacitance. When the WiFi module transmits (200mA spike for 5ms), the 3.3V rail dips by 200mV. MCU ADC readings become noisy. Communication packets are corrupted during TX bursts.
KiCad: Group bulk capacitors near regulators in schematic for visual clarity. Add notes indicating placement priority. Use schematic text to show capacitance budget.
Altium: Use Room definitions to associate bulk caps with their regulators. PDN Analyzer can verify impedance targets are met.
OrCAD: Place bulk caps on same schematic page as regulator circuit. Add placement notes. Use PSpice to simulate load transient response.
The capacitor value strategy defines a systematic approach to selecting decoupling capacitor values that provide low impedance across a wide frequency range. The classic pattern uses a combination: 100nF for high-frequency decoupling (effective 10MHz-200MHz), 10uF for medium-frequency (100kHz-10MHz), and optionally 1nF-10nF for very high frequency (>200MHz in GHz digital designs). Each value covers a specific frequency decade.
The goal is to create a low-impedance power delivery network (PDN) from DC up to the highest switching frequency in the design.
A single capacitor value cannot cover all frequencies. At its self-resonant frequency (SRF), a capacitor has minimum impedance - but above SRF, it becomes inductive and impedance rises. By paralleling multiple values, each with a different SRF, the combined impedance stays low across a wider bandwidth. Without this strategy, there are "gaps" in the impedance curve where noise cannot be filtered, appearing as specific frequency spikes in EMI measurements.
STM32H7 running at 480MHz - power pin decoupling strategy:
Per VDD pin: 100nF X7R 0402 (SRF ~100MHz) + 10nF X7R 0201 (SRF ~400MHz) Per cluster: 4.7uF X5R 0805 (SRF ~2MHz - mid frequency storage) Rail total: 2x 22uF X5R 1206 (bulk - regulator output stability) Frequency coverage: DC - 1MHz: 22uF bulk caps dominate 1MHz - 10MHz: 4.7uF caps effective 10MHz - 200MHz: 100nF caps effective 200MHz - 1GHz: 10nF caps effective Result: Low impedance from DC to 1GHz
Only 100nF caps everywhere: Designer uses only 100nF 0603 caps for all decoupling. At 1MHz (where MCU draws significant switching current), the 100nF cap's impedance is 1.6 ohms - too high for effective decoupling. No bulk caps fill this gap. Rail has 50mV ripple at 1MHz corresponding to regulator load transient response. Also, above 200MHz, the 0603 body is inductive and provides no decoupling for the 480MHz MCU clock harmonics.
KiCad: Use Murata SimSurfing or TDK SEAT tools online to verify capacitor impedance vs. frequency for your specific parts. Document strategy in schematic notes.
Altium: PDN Analyzer can import actual capacitor S-parameter models and show combined PDN impedance. Verify target impedance is met across frequency.
OrCAD: Use PSpice with manufacturer SPICE models (including ESR and ESL) to plot combined impedance vs. frequency. Many manufacturers provide downloadable models.
Ferrite beads are frequency-dependent resistors that provide increasing impedance at high frequencies. They are placed in series with power supply lines feeding analog circuits (ADCs, DACs, PLLs, analog sensors) to isolate sensitive analog power from noisy digital power. The ferrite bead, combined with decoupling capacitors on the analog side, forms a low-pass Pi-filter that blocks high-frequency switching noise.
A typical implementation: VDD_DIGITAL -- [Ferrite Bead] -- VDD_ANALOG, with caps on both sides of the ferrite.
Digital circuits inject noise onto power rails at clock frequency harmonics (often 10MHz-1GHz). Without isolation, this noise directly degrades analog performance: ADC readings become noisy (reducing effective number of bits), PLL jitter increases (causing clock skew), and audio circuits develop audible interference. A well-placed ferrite bead can improve ADC SNR by 6-20dB and reduce PLL jitter by 50% or more.
STM32 VDDA supply isolation:
VCC_3V3 rail --- [BLM18PG121] --- VDDA pin
(120 ohm @ 100MHz, 0.05 ohm DC, 2A rated)
Capacitors:
- Before ferrite: 100nF X7R (part of digital decoupling)
- After ferrite: 1uF X7R + 100nF X7R (analog supply reservoir)
Result: 40dB attenuation of 100MHz+ digital noise on analog supply.
ADC achieves 11.5 ENOB vs. 10.2 ENOB without the ferrite bead.
No analog isolation: STM32 VDDA pin connected directly to VDD_3V3 with only a 100nF cap. The 168MHz CPU clock and its harmonics (336MHz, 504MHz) couple directly to the ADC power supply. ADC readings on a DC voltage show +/- 15 LSB noise (vs. +/- 2 LSB with proper isolation). 12-bit ADC effectively becomes 9-bit. Temperature sensor readings jump +/- 3 degrees.
KiCad: Add ferrite bead symbols (typically from Device library, "Ferrite_Bead" or "L" with ferrite type). Verify correct part in BOM matches required impedance spec.
Altium: Use manufacturer simulation tools to select ferrite bead. Import impedance vs. frequency data into PDN analysis. Verify attenuation at target frequency.
OrCAD: Model ferrite bead as frequency-dependent impedance in PSpice (use manufacturer SPICE models). Simulate noise attenuation with AC analysis sweep.
Equivalent Series Resistance (ESR) determines how effectively a capacitor can supply transient current. At high frequencies, capacitor impedance is dominated by ESR (not capacitance). For high-speed digital circuits (>100MHz clocks), low-ESR ceramic capacitors (MLCC) are essential because their ESR of 5-50 milliohms allows them to supply current spikes without significant voltage drop. Higher-ESR electrolytics (50-500 milliohms) are ineffective at high frequencies.
Key relationship: Voltage drop during transient = ESR x Peak_transient_current.
When a 200MHz FPGA switches 100 I/O pins simultaneously, it draws a current spike of several amps for sub-nanosecond duration. The decoupling cap must supply this current with minimal voltage drop. With ESR of 5mOhm: V_drop = 0.005 * 2A = 10mV (acceptable). With ESR of 200mOhm (electrolytic): V_drop = 0.2 * 2A = 400mV (causes logic failures on a 1.0V core rail). ESR directly determines noise floor on power rails.
DDR3 VDDQ (1.5V) decoupling:
Requirement: Z_target = 50mV / 3A = 16.7 mOhm at 400MHz (DDR3-1600) Solution: - 12x 100nF X7R 0402 MLCC (ESR: 8mOhm each, parallel: 0.67mOhm) - 4x 10nF X7R 0201 MLCC (ESR: 15mOhm each, parallel: 3.75mOhm, effective above 300MHz) - 2x 22uF X5R 0805 MLCC (bulk storage for medium frequency) Combined PDN impedance at 400MHz: ~3 mOhm (well below 16.7mOhm target) All ceramic - no electrolytic used in high-frequency bypass role.
Electrolytic for high-speed: Designer uses 470uF/6.3V aluminum electrolytic capacitor (ESR: 150mOhm) as the primary decoupling for a DDR3 VDDQ rail. At 400MHz, the electrolytic is completely inductive (acts as an open circuit). Its 150mOhm ESR means even at lower frequencies, it cannot deliver transient current without significant voltage drop. DDR3 memory has timing violations during burst writes.
KiCad: Specify capacitor part numbers (not just values) in schematic to lock in ESR characteristics. Use manufacturer part numbers in footprint/BOM fields.
Altium: Use manufacturer libraries with embedded ESR data. PDN Analyzer uses this data for impedance calculations. Specify exact MPN in BOM.
OrCAD: Attach manufacturer SPICE models (include ESR/ESL parasitics) to capacitor symbols. AC analysis will show actual impedance including parasitic effects.
Large ICs (MCUs, FPGAs, SoCs) have multiple power pins that must EACH have dedicated decoupling capacitors. This is not optional - it is specified in every IC datasheet's application notes. Each VDD/VCCO/VCCINT pin has its own current path that must be decoupled independently. Sharing a single cap between multiple power pins defeats the purpose of having multiple pins.
Example: An STM32F407 in LQFP100 package has 7 VDD pins, 1 VDDA pin, 1 VBAT pin, and 2 VCAP pins - requiring 11+ decoupling capacitors minimum.
Multiple power pins exist because a single pin cannot provide enough current for the entire IC (due to bond wire inductance and current capacity). Each pin serves a specific internal power domain. If pins share decoupling, current flows through internal bond wires to reach poorly-decoupled pins, adding inductance and causing internal ground bounce. The IC manufacturer designed multiple pins for a reason - respect that design intent.
STM32F407 LQFP100 - complete decoupling scheme:
Pin 11 (VDD): 100nF X7R 0402 Pin 19 (VDD): 100nF X7R 0402 Pin 28 (VDD): 100nF X7R 0402 Pin 50 (VDD): 100nF X7R 0402 Pin 75 (VDD): 100nF X7R 0402 Pin 100 (VDD): 100nF X7R 0402 Pin 22 (VDDA): 1uF + 100nF (behind ferrite bead) Pin 21 (VREF+): 1uF + 100nF (behind ferrite bead) Pin 6 (VBAT): 100nF + 1uF Shared bulk: 4.7uF X5R 0805 (one per pair of VDD pins) TOTAL: 13 capacitors for one IC (correct per ST guidelines)
Shared decoupling: Same STM32F407 with only TWO 100nF capacitors total, placed "near the IC." Six VDD pins share two caps. VDDA connects directly to VDD with no ferrite or separate cap. VBAT has no capacitor. Result: 40mV power noise on VDD (vs. 10mV target), ADC ENOB reduced by 3 bits, PLL output has 50ps jitter (vs. 15ps spec), RTC loses time during flash write operations.
KiCad: Count caps in schematic vs. power pins in datasheet pinout table. Use text annotations listing each pin's assigned capacitor. In layout, use ratsnest to verify connections.
Altium: Use Component Properties to document which cap serves which pin. In PCB, verify each power pin has a short, direct connection to its dedicated capacitor pad.
OrCAD: Create a cross-reference table in schematic notes showing pin-to-capacitor assignments. Verify in layout that physical placement matches intent.