Tutorial: Module 2.1 - Impedance Control

Checkpoint 2.1.1: Target Impedance Defined Per Interface Critical

Every high-speed interface on the PCB must have a clearly defined target characteristic impedance. This value is determined by the interface specification and must be documented in the design constraints before routing begins.

Why This Matters

Impedance mismatches cause signal reflections, which degrade signal quality, increase jitter, and can cause bit errors. A 10% impedance mismatch results in approximately 5% reflected energy, which compounds at every discontinuity in the channel.

Common Interface Impedance Targets

Interface	Single-Ended (ohm)	Differential (ohm)	Tolerance
DDR4 Data/Address	40	80 (DQ/DQS)	+/- 10%
DDR5 Data	40	80	+/- 7%
PCIe Gen3/Gen4	-	85	+/- 10%
PCIe Gen5/Gen6	-	85	+/- 5%
USB 2.0	-	90	+/- 10%
USB 3.x/USB4	-	85	+/- 10%
HDMI 2.1	-	100	+/- 10%
Ethernet 10GBASE-KR	-	100	+/- 10%
LVDS	-	100	+/- 10%
SPI (>50 MHz)	50	-	+/- 10%
RGMII	50	-	+/- 10%
SATA III	-	85	+/- 10%

Step-by-Step Verification

Obtain the interface specification document (JEDEC, PCI-SIG, USB-IF, etc.) for each high-speed bus on your design.
Create an impedance requirements table listing every controlled-impedance net class.
Cross-reference the schematic net names with the impedance table to ensure no interface is missed.
Document the target Zo in your PCB constraints file or design rules.
Verify that your EDA tool has the correct impedance rules applied to each net class.

DDR4 Design Constraint Document:

Net Class: DDR4_DQ - Target Zo: 40 ohm single-ended, Zdiff: 80 ohm

Net Class: DDR4_CLK - Target Zdiff: 80 ohm differential

Net Class: DDR4_ADDR - Target Zo: 40 ohm single-ended

Stackup layer assignment: L3 (stripline, reference GND on L2 and L4)

Engineer routes DDR4 signals on any available layer without documenting impedance targets. The fab house uses default 50 ohm trace widths. DDR4 requires 40 ohm single-ended, causing 20% impedance mismatch and unreliable memory training.

Cadence Allegro: Set impedance constraints in Constraint Manager > Physical > Impedance. Assign to net classes under Electrical Rules.

Altium Designer: Use Design Rules > Routing > Impedance. Create rules per net class with target Zo and tolerance.

HyperLynx: Import stackup from EDA tool, then verify impedance matches design intent in LineSim stackup editor.

Checkpoint 2.1.2: Stackup Supports Controlled Impedance Critical

The PCB layer stackup must be designed to support all required impedance targets simultaneously. The combination of dielectric thickness, dielectric constant (Dk), copper weight, and trace geometry must allow achievable trace widths for all impedance targets.

Stackup Design Parameters

Parameter	Effect on Impedance	Typical Range
Dielectric Height (H)	Increasing H raises Zo	3-10 mil (75-250 um)
Dielectric Constant (Dk/Er)	Increasing Er lowers Zo	3.2-4.5 (FR4 range)
Trace Width (W)	Increasing W lowers Zo	3-12 mil (75-300 um)
Trace Thickness (T)	Increasing T slightly lowers Zo	0.5-2.1 mil (12-53 um)
Solder Mask (Sm)	Solder mask lowers Zo by 2-3 ohm on outer layers	0.5-1.5 mil thickness

Example: 8-Layer Stackup for DDR4 + PCIe

Layer   Type        Material        Thickness   Dk      Purpose
-----------------------------------------------------------------------
L1      Signal      1oz Cu          1.4 mil     -       Components, short SE traces
        Prepreg     1080            3.5 mil     4.2
L2      GND Plane   1oz Cu          1.4 mil     -       Reference for L1 and L3
        Core        2116            5.0 mil     4.3
L3      Signal      0.5oz Cu        0.7 mil     -       DDR4 DQ/DQS (stripline)
        Prepreg     1080            3.5 mil     4.2
L4      Power       1oz Cu          1.4 mil     -       VDD planes
        Core        2116            20.0 mil    4.3     (mechanical core)
L5      Power       1oz Cu          1.4 mil     -       VDD planes
        Prepreg     1080            3.5 mil     4.2
L6      Signal      0.5oz Cu        0.7 mil     -       PCIe differential (stripline)
        Core        2116            5.0 mil     4.3
L7      GND Plane   1oz Cu          1.4 mil     -       Reference for L6 and L8
        Prepreg     1080            3.5 mil     4.2
L8      Signal      1oz Cu          1.4 mil     -       Components, short SE traces
-----------------------------------------------------------------------
Total board thickness: ~62 mil (1.57mm)

Impedance Results (field solver calculated):
L1 Microstrip:  50 ohm = 5.2 mil trace, 100 ohm diff = 4.5 mil trace, 5.5 mil space
L3 Stripline:   40 ohm = 5.8 mil trace, 80 ohm diff = 4.8 mil trace, 5.0 mil space
L6 Stripline:   42.5 ohm SE, 85 ohm diff = 4.2 mil trace, 6.0 mil space

Step-by-Step Verification

List all impedance targets needed (from Checkpoint 2.1.1).
Work with your fab house to select appropriate materials (Dk, Df at frequency of interest).
Use a 2D field solver to calculate trace widths for each impedance target on each signal layer.
Verify that calculated trace widths are manufacturable (minimum 3 mil for standard, 2.5 mil for HDI).
Check that trace widths are compatible with component pad sizes and BGA fanout requirements.
Confirm the total board thickness is within acceptable range (typically 1.0-2.4 mm).
Get fabricator's impedance sign-off on the stackup before starting layout.

Proper stackup coordination: The designer sends a proposed stackup to the fabricator (e.g., JLCPCB, TTM, Sanmina) requesting impedance calculations. The fab returns confirmed Dk values at the operating frequency (e.g., Dk=3.9 at 5 GHz for Megtron 6) and verified trace widths for all target impedances.

Designer uses generic FR4 Dk=4.4 for impedance calculations. Actual Dk at 3 GHz is 4.0. The 10% Dk error translates to approximately 5% impedance error, consuming half the impedance budget before manufacturing tolerances are considered.

Dk varies with frequency: FR4 Dk ranges from 4.5 at 100 MHz to 3.8 at 10 GHz. Always use Dk at the signal's fundamental frequency (or Nyquist frequency for digital signals).

Prepreg resin content: Resin-rich prepreg has lower Dk (more resin, less glass). Verify which prepreg style your fab uses - 1080, 2116, and 7628 all have different Dk values.

Etch factor: Trapezoidal trace cross-section after etching lowers impedance by 1-3 ohm compared to rectangular model. Field solvers should model this.

Polar Si9000: Industry-standard impedance calculator. Supports microstrip, stripline, coplanar, and differential configurations. Model the trapezoidal etch profile for accuracy.

Cadence Allegro/Sigrity: Use PowerSI for stackup design with integrated 2D field solver. Set Dk/Df frequency-dependent models (Wideband Debye, Djordjevic-Sarkar).

Ansys HFSS: For critical applications, run a 3D cross-section simulation to verify impedance including surface roughness effects (Huray or Hammerstad model).

Checkpoint 2.1.3: Trace Width Calculated for Target Zo Critical

Trace widths must be calculated using electromagnetic field solvers or validated closed-form equations. The calculations must account for the actual stackup materials, copper weight, and manufacturing processes.

Microstrip Impedance Formula (IPC-2141 Approximation)

Outer Layer Microstrip (W/H ≤ 1):

Zo = (60 / sqrt(Er_eff)) * ln(8H/W + W/(4H))

Er_eff = (Er + 1)/2 + ((Er - 1)/2) * (1 / sqrt(1 + 12H/W))

Outer Layer Microstrip (W/H ≥ 1):

Zo = (120 * pi) / (sqrt(Er_eff) * (W/H + 1.393 + 0.667 * ln(W/H + 1.444)))

Where: H = dielectric height, W = trace width, Er = dielectric constant, T = trace thickness

Thickness correction (for finite T):

W_eff = W + (T/pi) * (1 + ln(4*pi*W/T)) [for microstrip]

Stripline Impedance Formula

Centered Stripline (symmetric):

Zo = (60 / sqrt(Er)) * ln(4B / (0.67 * pi * (0.8W + T)))

Offset Stripline (asymmetric):

Zo = (60 / sqrt(Er)) * ln(4 / (0.67 * pi * We * (1/B1 + 1/B2)))

We = W + (T/pi) * (1 + ln(4*pi*W/T))

Where: B = total dielectric between planes, B1/B2 = distance to each reference plane

W = trace width, T = copper thickness, Er = dielectric constant

Differential Impedance Formulas

Edge-Coupled Microstrip Differential:

Zdiff = 2 * Zo * (1 - 0.48 * exp(-0.96 * S/H))

Edge-Coupled Stripline Differential:

Zdiff = 2 * Zo * (1 - 0.347 * exp(-2.9 * S/B))

Where: S = edge-to-edge spacing between differential traces

Zo = single-ended impedance of one trace in isolation

H = dielectric height (microstrip), B = total dielectric thickness (stripline)

Worked Example: 50 ohm Microstrip on Outer Layer

Given:
  Er = 4.2 (1080 prepreg at 1 GHz)
  H = 3.5 mil (prepreg thickness to ground plane)
  T = 1.4 mil (1oz copper after plating)
  Solder mask thickness = 1.0 mil, Dk_mask = 3.5

Step 1: Initial calculation without solder mask
  Target: 50 ohm
  Using W/H >= 1 formula iteratively:
  Try W = 5.2 mil: W/H = 5.2/3.5 = 1.49
  Er_eff = (4.2+1)/2 + ((4.2-1)/2) * (1/sqrt(1+12*3.5/5.2))
  Er_eff = 2.6 + 1.6 * (1/sqrt(9.08)) = 2.6 + 0.531 = 3.131
  Zo = (120*pi) / (sqrt(3.131) * (1.49 + 1.393 + 0.667*ln(1.49+1.444)))
  Zo = 376.99 / (1.77 * (1.49 + 1.393 + 0.667*ln(2.934)))
  Zo = 376.99 / (1.77 * (1.49 + 1.393 + 0.718))
  Zo = 376.99 / (1.77 * 3.601) = 376.99 / 6.374 = 59.1 ohm (too high)

  Try W = 6.5 mil: W/H = 6.5/3.5 = 1.857
  Er_eff = 2.6 + 1.6 * (1/sqrt(1+12*0.538)) = 2.6 + 1.6*(1/sqrt(7.46)) = 2.6+0.586 = 3.186
  Zo = 376.99 / (1.785 * (1.857 + 1.393 + 0.667*ln(3.301)))
  Zo = 376.99 / (1.785 * (1.857 + 1.393 + 0.796))
  Zo = 376.99 / (1.785 * 4.046) = 376.99 / 7.222 = 52.2 ohm

Step 2: Apply solder mask correction (-2 to -3 ohm typical)
  With solder mask: Zo approximately 50.0 ohm

Step 3: Verify with field solver result
  Polar Si9000 result: W = 6.4 mil gives 50.1 ohm (matches within 1%)

CONCLUSION: Use W = 6.5 mil (0.165 mm) for 50 ohm microstrip on L1

Interactive Trace Width Calculator

Calculator: Enter your stackup parameters to calculate the required trace width for a target impedance. Uses IPC-2141 microstrip and stripline approximations.

Topology

Target Zo (Ω)

Dielectric Constant (Er)

Dielectric Height H (mil)

Copper Thickness T (mil)

Never rely solely on formulas: Closed-form equations are approximations (typically within 2-5%). Always verify with a 2D field solver for production designs. Formulas are useful for initial estimates and sanity checks.

Copper roughness effect: At frequencies above 3 GHz, copper surface roughness (Rz typically 3-6 um for standard oxide treatment) increases effective inductance and raises impedance by 1-3 ohm. Include roughness models in simulations.

Glass weave effect: FR4 has non-uniform Dk due to glass weave pattern. Dk under glass bundles is approximately 6.0, while Dk in resin-rich pockets is approximately 3.2. For sensitive signals (>5 Gbps), use spread-glass materials or route at angles to the weave.

Checkpoint 2.1.4: Impedance Tolerance +/-10% Major

The total impedance tolerance budget must account for manufacturing variations, material tolerances, and environmental factors. The commonly specified +/-10% overall tolerance must be broken down into constituent contributors.

Impedance Tolerance Budget Breakdown

Contributor	Typical Variation	Effect on Zo
Dielectric thickness (H)	+/- 0.5 mil	+/- 3-5%
Trace width (W) etch tolerance	+/- 0.5 mil	+/- 2-4%
Dk material variation	+/- 0.1-0.2	+/- 1-3%
Copper thickness variation	+/- 0.2 mil	+/- 0.5-1%
Temperature (-40 to +85C)	Dk shifts +0.1-0.3	-1 to -2%
Resin content variation	+/- 2-3%	+/- 0.5-1%

RSS (Root Sum Square) Tolerance Calculation

Total tolerance = sqrt(sum of individual tolerances squared)

Example: sqrt(4%^2 + 3%^2 + 2%^2 + 1%^2 + 1.5%^2 + 0.5%^2)

= sqrt(16 + 9 + 4 + 1 + 2.25 + 0.25) = sqrt(32.5) = 5.7%

With 3-sigma coverage: approximately 5.7% (within 10% budget)

Step-by-Step Verification

Request your fabricator's manufacturing capability data (etch tolerance, dielectric thickness tolerance, registration accuracy).
Build a tolerance stackup using RSS method for each impedance target.
If total RSS tolerance exceeds the interface specification, tighten individual contributors (better material, tighter etch process, or reduce design sensitivity by increasing dielectric height).
Specify impedance testing requirements on fabrication drawing (typically TDR measurement of test coupons).
Define acceptance criteria: typically +/-10% for standard designs, +/-5% for critical SerDes channels.

Fabrication note: "Controlled impedance per IPC-2141. All impedance values to be verified via TDR measurement of test coupons. Accept: 50 ohm +/-10% (45-55 ohm). Reject lot if any coupon measures outside 42-58 ohm (+/-15%)."

Fab drawing states "50 ohm controlled impedance" without specifying tolerance, measurement method, or acceptance criteria. Fabricator delivers boards with 43 ohm impedance (outside spec), but no test data exists to catch it.

Tolerance stacking: If your design has minimal margin and multiple interfaces, avoid worst-case analysis (arithmetic sum) - it is overly pessimistic. Use RSS for independent variables. But be aware that some variables may be correlated (e.g., all traces on the same layer will shift together).

Inner layer vs outer layer tolerance: Inner layer (stripline) impedance is typically better controlled (+/-7%) than outer layer (microstrip) (+/-10%) because inner layer dielectric thickness is set by the core material which is pre-manufactured to tight tolerances.

Checkpoint 2.1.5: Reference Plane Identified Critical

Every controlled-impedance trace must have a clearly identified reference plane (ground or power). The impedance value depends on the distance to this reference plane, and the reference plane provides the return current path.

Reference Plane Requirements

The reference plane must be continuous (no splits, slots, or gaps) under the signal trace.
Ground planes are preferred over power planes as references because they have lower inductance and no switching noise.
For stripline, both adjacent planes serve as references - identify BOTH.
If a power plane is used as reference, it must be well-decoupled to be AC ground at the frequency of interest.

Layer Assignment Strategy

Recommended 8-Layer Assignment:
Layer   Function          Reference Planes
L1      Signal (ustrip)   Referenced to L2 (GND)
L2      GND              -
L3      Signal (strip)    Referenced to L2 (GND) above and L4 (PWR) below
L4      Power            -
L5      Power            -
L6      Signal (strip)    Referenced to L5 (PWR) above and L7 (GND) below
L7      GND              -
L8      Signal (ustrip)   Referenced to L7 (GND)

Key Rules:
- L3 signals: primary reference is L2 (GND) - preferred
- L6 signals: primary reference is L7 (GND) - preferred
- Power planes (L4, L5) as secondary references require adequate decoupling

Step-by-Step Verification

For each signal layer, identify the adjacent plane layer(s) that serve as impedance reference.
Verify that ground plane layers have >90% copper fill (no excessive splits or cutouts).
Check that power plane references have decoupling capacitors providing low impedance at the signal frequencies.
Document the reference assignment in the stackup drawing and constraint system.
Verify in layout that no signal trace crosses a plane split on its reference layer.

DDR4 data signals routed on L3 with L2 (solid GND plane) as the reference. The L2 ground plane has no splits or voids under the DDR4 routing area. L4 (power) provides symmetric stripline but is a secondary reference. Decoupling caps on L4 ensure it is AC ground at DDR4 data rates.

High-speed signal routed on L3 crosses over a split in the L2 ground plane (split separates analog and digital grounds). At the split crossing, the reference distance changes from 3.5 mil to effectively infinite, causing a massive impedance discontinuity and EMI radiation.

Cadence Allegro: Use "Shape > Check" to verify plane continuity. Run DRC with "Reference Plane Check" enabled to flag signals crossing plane voids.

Altium Designer: Use the "Split Plane" design rule to check reference plane integrity. The Signal Integrity analyzer reports reference layer for each net.

Sigrity PowerSI: Import layout and visualize return current density on planes. High current density at plane edges indicates problematic return paths.

Checkpoint 2.1.6: Impedance Discontinuities Minimized Major

Every geometric change along a signal path creates an impedance discontinuity that causes reflections. The cumulative effect of multiple small discontinuities can be worse than a single large one due to constructive interference of reflected waves.

Common Sources of Impedance Discontinuity

Source	Typical dZ	Mitigation
Via transition (signal via)	+5 to +15 ohm	Add ground vias nearby, use via back-drill
BGA pad/fanout	-5 to -10 ohm (capacitive)	Reduce pad size, neck-down trace at pad
Connector footprint	-3 to +5 ohm	Match connector Zo, optimize footprint
Width change at plane split crossing	+10 to +30 ohm	Avoid! Use stitching caps or reroute
Solder mask opening	+2 to +3 ohm	Account in calculation, use mask-defined pads
Test point pad	-2 to -5 ohm	Minimize pad size, use via-in-pad test points
AC coupling capacitor	Variable	Use 0201/0402 size, minimize pad area
Trace width change	Proportional to dW	Taper gradually, minimize length of narrow sections

Via Discontinuity Modeling

Via stub capacitance (approximate):

C_via = (1.41 * Er * T_plate * D_pad) / (D_clearance - D_pad)

Where: T_plate = stub length, D_pad = via pad diameter, D_clearance = antipad diameter

Via inductance (approximate):

L_via = 5.08 * h * (ln(4h/d) + 1) [nH]

Where: h = via length in inches, d = via drill diameter in inches

Via characteristic impedance:

Zo_via = sqrt(L_via / C_via)

Target: Match Zo_via to trace Zo (typically requires Zo_via = 45-55 ohm)

Step-by-Step Verification

Run TDR simulation on critical nets using IBIS/SPICE models to identify impedance discontinuities.
Catalog all discontinuities along each critical signal path (source pad, fanout via, trace, connector, etc.).
Quantify each discontinuity magnitude and duration (electrical length).
For discontinuities > 5% of Zo, implement mitigation (ground vias, pad size reduction, back-drill).
Re-simulate after mitigation to verify improvement.
Set acceptance criteria: TDR impedance profile within +/-10% of target for entire channel.

Via optimization for 10 Gbps PCIe: Signal via drill = 8 mil, pad = 16 mil, antipad = 28 mil. Two ground vias (8 mil drill) placed 25 mil from signal via. Via stub back-drilled to within 10 mil of signal layer. Simulated via Zo = 48 ohm (within 10% of 50 ohm target). Discontinuity duration = 5 ps (well below 1/10 rise time of 33 ps for PCIe Gen3).

Signal via uses 12 mil drill, 24 mil pad, standard 40 mil antipad. No ground vias nearby. Via stub extends full board thickness (62 mil). Via Zo = 28 ohm with 8 pF stub capacitance. Creates a -15 dB resonance at 4.7 GHz, right in the PCIe Gen3 frequency band.

Keysight ADS: Use the TDR simulation in the Signal Integrity toolkit. Import via models from HFSS or use built-in via models. Plot impedance vs. distance for full channel.

Ansys HFSS: Model the complete via structure in 3D. Extract S-parameters and convert to impedance profile. Optimize antipad size and ground via placement.

Sigrity 3D Solver: Use PowerSI 3D for via modeling within the actual board stackup. Includes effects of nearby vias and plane cavity resonances.

Checkpoint 2.1.7: Test Coupons Specified Major

Test coupons are dedicated impedance verification structures fabricated on the same panel as the production PCB. They provide the only reliable method of verifying that the manufactured board meets impedance specifications.

Test Coupon Requirements

Location: Place coupons in the panel border (waste area), not on the PCB itself.
Length: Minimum 6 inches (150 mm) for TDR measurement, 2 inches minimum for each impedance structure.
Configurations: Include all unique impedance targets (microstrip, stripline, differential pairs on each signal layer).
Launch pads: Design for your measurement system (typical: SMA launch for RF probes or TDR).
Quantity: Minimum 2 coupons per panel, preferably at opposite corners to check uniformity.

Coupon Design Specifications

Typical Impedance Test Coupon Content:
1. Single-ended microstrip (50 ohm) - L1 referenced to L2
2. Differential microstrip (100 ohm) - L1 referenced to L2
3. Single-ended stripline (50 ohm) - L3 referenced to L2/L4
4. Differential stripline (85 ohm) - L6 referenced to L5/L7
5. Single-ended stripline (40 ohm) - L3 for DDR4
6. Differential stripline (80 ohm) - L3 for DDR4 DQS

Each structure includes:
- Launch pad (50x50 mil pad with ground pads for GSG probe)
- Transition from launch to target trace width (tapered)
- Minimum 2-inch controlled-impedance section
- Termination or open for TDR reflection measurement

Measurement Method: TDR (Time Domain Reflectometry)
- Equipment: Tektronix DSA8300 or Keysight N1930B
- Rise time: 20 ps or faster
- Calibration: SOLT or TRL using reference standards
- Measurement window: Steady-state region of TDR trace (after launch, before end reflection)

Step-by-Step Verification

Identify all unique impedance structures in your design (different Zo, different layers, different trace types).
Design test coupon structures for each unique impedance (refer to IPC-2141 Appendix A for standard coupon designs).
Include GSG (Ground-Signal-Ground) probe launch pads compatible with your TDR measurement system.
Add the coupons to your panel drawing with clear identification labels.
Specify measurement requirements on the fabrication drawing: equipment type, rise time, acceptance criteria.
Request TDR measurement report from fabricator with each production lot.

Fabrication drawing note: "Impedance test coupons per drawing XXXX-COUPON-01. Measure all structures using TDR with rise time ≤ 25 ps. Report measured impedance for each structure. Acceptance: +/-10% of nominal. Provide TDR waveform plots with shipment. One coupon set per panel, minimum 2 panels per lot measured."

No test coupons included in the panel. Fabricator performs no impedance verification. First article boards fail signal integrity testing. Root cause: dielectric thickness was 10% too thin due to pressing process variation, resulting in 45 ohm instead of 50 ohm. Issue not caught until functional testing, causing 4-week schedule slip.

Coupon vs. actual board: Coupons measure the process capability but cannot catch localized defects on the actual PCB (voids, delamination, etch defects). For highest reliability, also perform TDR on actual board traces at designated test points.

Probe pad parasitics: Large probe pads create capacitive loading that affects TDR measurements. Use the calibration/de-embedding procedure to remove pad effects from the measurement.

Temperature effects: TDR measurements at 25C may not reflect impedance at operating temperature (85C). Dk increases approximately 0.5% per 10C, slightly lowering impedance.

IPC Standards: IPC-2141A "Design Guide for High-Speed Controlled Impedance Circuit Boards" provides standard coupon designs and measurement procedures.

Measurement Tools: Tektronix DSA8300 with 80E10B sampling module (9 ps rise time), Keysight N1930B Physical Layer Test System, or Molex/Temp-Flex impedance measurement fixtures.

De-embedding: Use TDR gating or AFR (Automatic Fixture Removal) to separate the test fixture effects from the DUT impedance.