Tutorial: Module 2.6 - SerDes & High-Speed Interfaces

Checkpoint 2.6.1: Channel Loss Budget (Insertion Loss) Critical

Insertion loss (IL) represents the total signal attenuation from transmitter to receiver. For SerDes links, the channel loss must be within the receiver's equalization capability. Excessive loss prevents the CDR from locking and causes unrecoverable bit errors.

Insertion Loss Budget by Interface

Interface	Data Rate	Nyquist Freq	Max IL at Nyquist	Max Channel Length (FR4)
PCIe Gen3	8 GT/s	4 GHz	-20 dB	~16 inches
PCIe Gen4	16 GT/s	8 GHz	-28 dB	~10 inches
PCIe Gen5	32 GT/s	16 GHz	-36 dB	~5 inches
USB 3.2 Gen1	5 GT/s	2.5 GHz	-15 dB	~14 inches
USB 3.2 Gen2	10 GT/s	5 GHz	-20 dB	~10 inches
USB4 Gen3	20 GT/s	10 GHz	-25 dB	~5 inches
SATA III	6 GT/s	3 GHz	-18 dB	~18 inches
10GBASE-KR	10.3125 Gbps	5.15 GHz	-23 dB	~12 inches
25GBASE-KR	25.78125 Gbps	12.9 GHz	-30 dB	~6 inches

Loss Contributors

Total insertion loss = Trace_loss + Via_loss + Connector_loss + AC_cap_loss

Trace loss (dominant contributor):

IL_trace(f) = -(alpha_d + alpha_c) * Length

alpha_d = dielectric loss = pi*f*sqrt(Er)*Df / c [Np/m]

alpha_c = conductor loss = Rs/(2*Zo*W) [Np/m] where Rs = sqrt(pi*f*mu*rho)

Approximate trace loss at Nyquist (dB/inch):

Standard FR4 (Dk=4.2, Df=0.02): ~ 1.0 dB/inch at 4 GHz, ~1.5 dB/inch at 8 GHz

Mid-loss (Megtron4, Df=0.008): ~ 0.6 dB/inch at 4 GHz, ~0.9 dB/inch at 8 GHz

Low-loss (Megtron6, Df=0.004): ~ 0.4 dB/inch at 4 GHz, ~0.6 dB/inch at 8 GHz

Ultra-low-loss (Megtron7, Df=0.002): ~ 0.3 dB/inch at 4 GHz, ~0.45 dB/inch at 8 GHz

Via loss (per via pair):

Well-designed via: 0.2-0.5 dB at Nyquist

Poor via (long stub): 1-3 dB at resonance frequency

Connector loss:

High-quality connector (Samtec, TE STRADA): 0.5-1.0 dB

Standard connector: 1.0-2.0 dB

AC coupling capacitor:

0402 100 nF (good layout): 0.1-0.2 dB

Worked Example: PCIe Gen4 Channel Budget

PCIe Gen4 x16 slot on motherboard:
  Data rate: 16 GT/s, Nyquist: 8 GHz
  Max allowed IL at 8 GHz: -28 dB

Channel path: CPU -> PCB trace -> via -> PCB trace -> connector -> add-in card trace -> GPU

Budget allocation:
  CPU package + BGA fanout:      1.5 dB
  Motherboard trace (6 inches, Megtron6): 6 * 0.6 = 3.6 dB
  Via transitions (2 pairs):     2 * 0.4 = 0.8 dB
  PCIe slot connector:           1.5 dB
  Add-in card trace (2 inches):  2 * 0.6 = 1.2 dB
  Add-in card vias + package:    2.0 dB
  AC coupling caps (2x):         0.3 dB
  -----------------------------------------
  Total:                         10.9 dB at 8 GHz

  10.9 dB < 28 dB max: PASS with 17 dB margin for equalization

  Note: The equalization margin allows the system to compensate for
  additional manufacturing variation and temperature effects.

Step-by-Step Verification

Identify the complete signal path from TX IC ball to RX IC ball (all segments, vias, connectors).
Calculate or simulate insertion loss for each segment at the Nyquist frequency.
Sum all losses to determine total channel insertion loss.
Compare against interface specification maximum IL (see table above).
If budget is tight: consider low-loss materials, back-drilling vias, or shorter routes.
After layout: extract S-parameters and verify IL stays within budget across full bandwidth.

PCIe Gen5 on server motherboard:

Material: Megtron 7 (Dk=3.4, Df=0.002) for signal layers adjacent to SerDes routes.

Trace length: 4 inches (minimized through optimal placement).

All vias back-drilled to within 8 mil of signal layer.

Total IL at 16 GHz: 12 dB (within 36 dB budget, providing 24 dB EQ margin).

PCIe Gen4 routed on standard FR4 (Df=0.020) for 10 inches. Trace loss alone: 10 * 1.5 dB/inch at 8 GHz = 15 dB. With vias and connector: 19 dB. While technically within the 28 dB limit, only 9 dB margin remains for equalization. Temperature variation and manufacturing tolerance can push this over the limit, causing intermittent link failures at high temperature.

Keysight ADS Channel Simulator: Import S-parameters and run statistical eye analysis with TX pre-emphasis and RX CTLE/DFE. Reports BER contours and margin.

Ansys HFSS/SIwave: Full 3D extraction of vias and transitions. Export broadband S-parameters for system simulation.

Cadence Sigrity: PowerSI for 2.5D extraction, SystemSI for channel simulation with equalization. Supports COM (Channel Operating Margin) calculation per IEEE 802.3.

Checkpoint 2.6.2: Return Loss (RL) Specification Critical

Return loss measures impedance matching quality. High return loss (in negative dB) indicates good matching. Poor return loss creates reflections that close the eye diagram and interfere with equalization.

Return Loss Requirements

Interface	RL Specification	Frequency Range
PCIe Gen3	< -10 dB (differential)	50 MHz to 4 GHz
PCIe Gen4	< -10 dB (differential)	50 MHz to 8 GHz
PCIe Gen5	< -12 dB (differential)	50 MHz to 16 GHz
USB 3.2	< -10 dB	100 MHz to 5 GHz
USB4	< -12 dB	100 MHz to 10 GHz
10GBASE-KR	< -10 dB	100 MHz to 5.15 GHz
SATA III	< -10 dB	100 MHz to 3 GHz

Return Loss Analysis

Return Loss from impedance mismatch:

RL = -20*log10(|rho|) = -20*log10(|(Zl - Zo)/(Zl + Zo)|)

Examples:

5% mismatch (Zl=52.5, Zo=50): RL = -20*log10(2.5/102.5) = 32 dB (excellent)

10% mismatch (Zl=55, Zo=50): RL = -20*log10(5/105) = 26 dB (good)

20% mismatch (Zl=60, Zo=50): RL = -20*log10(10/110) = 21 dB (marginal)

50% mismatch (Zl=75, Zo=50): RL = -20*log10(25/125) = 14 dB (poor)

Worst offenders for return loss:

1. Vias without back-drill (capacitive stub resonance)

2. Connector transitions (impedance mismatch at pads)

3. AC coupling capacitor pads (capacitive discontinuity)

4. BGA breakout area (pad-to-trace transition)

Step-by-Step Verification

After layout, extract S-parameters for each SerDes channel (full path TX to RX).
Plot Sdd11 (differential return loss at TX) and Sdd22 (at RX).
Verify RL is below specification limit across the entire frequency range.
Identify any resonant peaks (where RL exceeds limit) and trace to physical cause.
Common fixes: back-drill via stubs, optimize connector footprint, reduce pad sizes.
Re-extract and verify after layout modifications.

Via stub resonance: An undrilled via stub of length L creates a quarter-wave resonance at f_res = c/(4*L*sqrt(Er)). For a 50-mil stub in FR4: f_res = 3e8/(4*0.05*0.0254*sqrt(4.2)) = 14.4 GHz. This frequency falls within PCIe Gen5 bandwidth! Back-drilling removes the stub and eliminates the resonance.

Return loss vs. impedance tolerance: A 10% impedance tolerance (+/-5 ohm on 50 ohm) gives worst-case RL of 26 dB. This is fine for most interfaces. But if multiple discontinuities are in phase (separated by half-wavelength), their reflections add constructively, degrading RL further.

Checkpoint 2.6.3: Eye Diagram Compliance Critical

The eye diagram is the ultimate measure of channel quality. It shows the superposition of all possible bit transitions and reveals the available timing and voltage margin at the receiver. The eye must remain open (clear of the mask) at the target BER.

Eye Mask Specifications

PCIe Gen3 (8 GT/s) Eye Mask at Receiver (after equalization):
  Unit Interval: 125 ps
  Eye width (at BER=1e-12): > 0.3 UI = 37.5 ps
  Eye height (at BER=1e-12): > 15 mV (after CTLE)
  Mask definition: Hexagonal mask with corners at:
    (0.25 UI, 0), (0.4 UI, +Vmask), (0.6 UI, +Vmask), (0.75 UI, 0)
    Mirrored for negative eye

PCIe Gen4 (16 GT/s):
  Unit Interval: 62.5 ps
  Eye width: > 0.3 UI = 18.75 ps
  Eye height: > 10 mV (after full equalization)
  Requires TX FIR (3-tap) + RX CTLE + RX DFE (up to 8 taps)

PCIe Gen5 (32 GT/s):
  Unit Interval: 31.25 ps
  Eye width: > 0.2 UI = 6.25 ps
  Eye height: > 5 mV (after full equalization)
  Requires TX FIR (3-tap) + RX CTLE (multiple stages) + RX DFE (16+ taps)

USB 3.2 Gen2 (10 GT/s):
  Unit Interval: 100 ps
  Eye width: > 0.4 UI = 40 ps
  Eye height: > 50 mV
  Measured at compliance point with test fixture de-embedded

Step-by-Step Eye Analysis

Extract channel S-parameters from post-layout simulation (include TX package, PCB, connector, RX package).
Import S-parameters into channel simulator (ADS, Sigrity SystemSI, or vendor tool).
Configure TX model: output voltage swing, rise time, jitter, pre-emphasis/de-emphasis settings.
Configure RX model: CTLE frequency response, DFE tap count and adaptation, CDR bandwidth.
Run statistical eye analysis (faster) or bit-by-bit simulation (more accurate for long patterns).
Overlay the specification eye mask on the simulated eye diagram.
Verify the eye is open and no bit sequences violate the mask at the target BER (typically 1e-12).
Report eye height, eye width, and BER bathtub curves.

Keysight ADS: Use the "Channel Simulation" workspace with SerDesDesign Kit. Import S-parameters, configure IBIS-AMI models for TX and RX, run statistical analysis. Supports COM calculation for IEEE compliance.

Cadence Sigrity SystemSI: End-to-end channel simulation with AMI model support. Generates eye diagrams, bathtub curves, and margin reports. Includes PCIe/USB compliance checkers.

Intel IBIST: Intel's channel simulation tool for PCIe compliance. Free for designs using Intel CPUs. Includes built-in TX/RX models for Intel silicon.

Checkpoint 2.6.4: TX De-emphasis/Pre-emphasis Major

TX equalization (pre-emphasis or de-emphasis) compensates for channel loss by boosting high-frequency content at the transmitter. This "pre-distorts" the signal so it arrives at the receiver with a more uniform frequency response.

TX FIR Filter Design

3-tap TX FIR filter (PCIe Gen3/4/5):

Output(n) = C(-1)*D(n+1) + C(0)*D(n) + C(+1)*D(n-1)

Where: C(-1) = pre-cursor, C(0) = main cursor, C(+1) = post-cursor

Constraint: |C(-1)| + |C(0)| + |C(+1)| = 1.0 (normalized)

De-emphasis (reduce amplitude after transition):

De-emphasis ratio = 20*log10(C(0) / (C(0) - |C(+1)|))

Example: C(-1)=0, C(0)=0.75, C(+1)=-0.25

De-emphasis = 20*log10(0.75/0.50) = 3.5 dB

Pre-emphasis (boost amplitude at transition):

First UI after transition: amplitude = C(0) + |C(+1)| (boosted)

Subsequent UIs: amplitude = C(0) - |C(+1)| (nominal)

Boost ratio = 20*log10((C(0)+|C(+1)|) / (C(0)-|C(+1)|))

PCIe Gen4 TX coefficient ranges:

C(-1): 0 to -0.2 (pre-cursor, for reflections)

C(0): 0.6 to 1.0 (main cursor)

C(+1): 0 to -0.35 (post-cursor, for ISI compensation)

Total de-emphasis range: 0 to 9.5 dB

Step-by-Step Configuration

Determine channel loss at Nyquist frequency from S-parameter extraction.
Rule of thumb: set de-emphasis approximately equal to half the channel loss at Nyquist.
For channel loss of 12 dB: start with 6 dB de-emphasis (C0=0.833, C+1=-0.167).
Run channel simulation sweeping TX coefficients to find optimal settings.
Verify TX output meets spec: voltage swing with pre/de-emphasis must stay within TX mask.
Document optimal TX settings for firmware/BIOS configuration.

Over-equalization: Too much de-emphasis reduces the signal amplitude at the receiver (the "de-emphasized" bits become too small). The optimal point maximizes eye opening, not just high-frequency boost.

Pre-cursor for reflections: The C(-1) pre-cursor tap compensates for pre-cursor ISI from reflections. If the channel has significant near-end reflections, increasing C(-1) can help. But for well-matched channels, C(-1)=0 is often optimal.

Checkpoint 2.6.5: RX Equalization (CTLE/DFE) Major

The receiver uses equalization to further compensate for channel loss. CTLE (Continuous Time Linear Equalizer) boosts high frequencies, while DFE (Decision Feedback Equalizer) removes post-cursor ISI without amplifying noise.

CTLE and DFE Characteristics

CTLE (analog peaking filter):

H_ctle(f) = (1 + j*f/fz) / (1 + j*f/fp)

DC gain: 0 dB (or slight attenuation)

Peaking at fp: gain = fz/fp (in dB: 20*log10(fp/fz))

Typical peaking range: 0 to 15 dB

Key CTLE parameters:

- Zero frequency (fz): typically Nyquist/4 to Nyquist/2

- Pole frequency (fp): typically Nyquist to 2*Nyquist

- Peaking gain: 0 to 15 dB (selectable in firmware)

DFE (digital, removes post-cursor ISI):

y(n) = x(n) - sum(h(k) * D(n-k)) for k=1 to N_taps

Where: h(k) = adapted tap weight, D(n-k) = previous decisions

Key advantage: DFE does not amplify noise (uses hard decisions)

Limitation: DFE cannot help with pre-cursor ISI or jitter

Typical DFE capability:

PCIe Gen3: No DFE required (CTLE only)

PCIe Gen4: 1-4 DFE taps

PCIe Gen5: 8-16 DFE taps

Each DFE tap can cancel approximately 3-5 dB of post-cursor ISI

When EQ Cannot Save the Channel

Excessive loss (>36 dB at Nyquist): Signal too small for CDR to lock reliably.
Resonant notch in IL: If IL has a deep null (from via stub resonance), EQ cannot recover the missing frequency content.
Excessive crosstalk: EQ amplifies crosstalk along with signal.
Poor return loss: Reflections create pre-cursor ISI that DFE cannot cancel.
Excessive jitter: Random jitter is not compensated by linear EQ.

Checkpoint 2.6.6: Via Optimization (Back-drilling) Critical

Via stubs act as open-circuited transmission line stubs that create quarter-wave resonances. At the resonant frequency, the stub presents a short circuit to the signal, creating a deep notch in the insertion loss. Back-drilling (controlled-depth drilling from the opposite side) removes the stub.

Via Stub Resonance Calculation

Quarter-wave resonance frequency:

f_res = c / (4 * L_stub * sqrt(Er))

Where: L_stub = stub length (distance from signal layer to end of via barrel)

Example - 62 mil board, signal on L3 (10 mil from top):

Stub length = 62 - 10 = 52 mil = 1.32 mm

f_res = 3e8 / (4 * 1.32e-3 * sqrt(4.2)) = 27.8 GHz

Third-harmonic resonance at: f_res/3 = 9.3 GHz

This affects PCIe Gen4 (Nyquist = 8 GHz) and Gen5 (16 GHz)!

With back-drill to 10 mil from signal layer:

Remaining stub = 10 mil = 0.254 mm

f_res = 3e8 / (4 * 0.254e-3 * sqrt(4.2)) = 144 GHz (far above any signal bandwidth)

Back-drill depth tolerance:

Typical fab tolerance: +/- 4 mil

Design target: drill to 8-10 mil above signal layer (leaves 4-14 mil worst case)

Worst case remaining stub (14 mil): f_res = 3e8/(4*0.356e-3*sqrt(4.2)) = 103 GHz (still fine)

Back-Drilling Requirements by Data Rate

Data Rate	Nyquist (GHz)	Max Stub (mil)	Back-Drill Needed?
< 5 GT/s	2.5	No limit practical	No
5-8 GT/s	2.5-4	60 mil	Usually no (unless board >80 mil)
8-16 GT/s	4-8	30 mil	Yes, for boards >40 mil thick
16-32 GT/s	8-16	15 mil	Yes, always
>32 GT/s	>16	8 mil	Yes, tight tolerance required

Alternative to Back-Drilling: Via Structure Design

1. Blind/buried vias: Only extend between required layers. No stub.
   Cost: 2-3x more expensive than through-hole vias.
   Used for: HDI designs, smartphone PCBs, some high-end servers.

2. Back-drilling (controlled depth): Drill from back side to remove stub.
   Cost: ~$0.05-0.10 per hole additional.
   Tolerance: +/- 4 mil depth control (standard), +/- 2 mil (advanced).
   Used for: Most server and networking boards, PCIe Gen4+.

3. Via aspect ratio optimization: Use thinner boards where possible.
   Reduces stub length naturally without additional processing.

4. Route on layers closest to the entry side of the via.
   If via enters from top: route on layers near top (L1-L4 of 16-layer).
   Minimal stub on entry side.

Step-by-Step Implementation

Identify all vias on SerDes signal paths (including AC coupling cap connections).
Calculate stub length for each via based on signal layer and total board thickness.
Determine maximum acceptable stub length from data rate (see table).
For vias exceeding the limit: specify back-drill depth in fabrication documentation.
Back-drill specification: "Drill from [side] to within [X] mil of layer [N]" (include tolerance).
Verify with fab house that back-drill tolerance is adequate for your design.
After fabrication: request cross-section verification of back-drill depth on first article.

PCIe Gen5 on 100-mil thick server board, signal on L4 (12 mil from top):

Via stub without back-drill: 100 - 12 = 88 mil (f_res = 4.1 GHz - directly in band!)

Back-drill specification: "Drill from bottom side to within 10 mil of L4. Tolerance +/-3 mil."

Worst case remaining stub: 10+3 = 13 mil (f_res = 89 GHz - safely above 16 GHz Nyquist)

Fab note: "Back-drill diameter = 12 mil (0.3mm). All SerDes signal vias per drawing note 7."

PCIe Gen4 (16 GT/s, Nyquist=8 GHz) on 93-mil board with signals on L3 (8 mil from top). Stub = 85 mil. Resonance at 5.4 GHz - directly in PCIe Gen4 band. IL shows a -25 dB notch at 5.4 GHz. The eye is completely closed at this frequency. Link fails to train above Gen2 speed (5 GT/s). Back-drilling was not specified because "it worked at Gen3" (which has Nyquist at 4 GHz, below the 5.4 GHz resonance).

Ansys HFSS: Model the via with and without back-drill in 3D. Compare S21 (insertion loss) to identify the stub resonance and verify its removal after back-drill. Include surrounding ground vias for accuracy.

Cadence Sigrity PowerSI: 3D via extraction includes stub effects automatically. Enable "back-drill" option in via model to simulate the improvement.

Polar Si9000: The newer versions include a via stub calculator that predicts resonant frequency from stub length and dielectric constant.