Tutorial: Module 2.8 - Analog & Mixed-Signal

Checkpoint 2.8.1: ADC/DAC Reference Integrity Critical

The voltage reference determines the absolute accuracy of ADC/DAC conversions. Any noise, drift, or error on the reference directly translates to measurement error. A reference noise of 1 LSB at the ADC's resolution makes the last bit meaningless.

Reference Noise Budget

LSB voltage (1 LSB):

V_LSB = V_ref / 2^N

12-bit, 3.3V ref: V_LSB = 3.3/4096 = 0.806 mV

16-bit, 4.096V ref: V_LSB = 4.096/65536 = 62.5 uV

24-bit, 2.5V ref: V_LSB = 2.5/16777216 = 0.149 uV

Reference noise must be < 0.5 LSB (RMS) for full resolution:

12-bit: noise < 403 uV RMS (relatively easy)

16-bit: noise < 31 uV RMS (requires careful design)

24-bit: noise < 0.075 uV RMS (extremely challenging - usually ADC limited)

Common voltage reference ICs and their noise:

TI REF5040 (4.096V): 3 uVpp (0.1-10 Hz), 8 uV RMS (wideband) - good for 16-bit

ADI ADR4540 (4.096V): 1.5 uVpp (0.1-10 Hz), 5 uV RMS - excellent for 16-bit

LTC6655-2.5 (2.5V): 0.625 uVpp (0.1-10 Hz), 2 uV RMS - suitable for 18-bit

MAX6126 (2.5V): 1.5 uVpp, 3 uV RMS - good for 16-bit

Total reference noise = sqrt(V_ref_noise^2 + V_PCB_coupled_noise^2 + V_PS_ripple^2)

PCB-coupled noise must be << reference IC noise to avoid degradation.

Target: PCB-coupled noise < 0.3 * V_ref_intrinsic_noise

Reference Layout Best Practices

Place voltage reference IC as close to the ADC/DAC VREF pin as possible (< 500 mil).
Decouple reference output with: 10 uF (bulk) + 1 uF (mid-freq) + 100 nF (high-freq) to local ground.
Use a dedicated copper pour (connected to ground plane) under the reference circuit.
Route VREF trace as wide as practical (10-20 mil) to reduce resistance and inductance.
Guard the VREF trace with ground traces on both sides (grounded every 100 mil).
Keep switching power supplies and digital buses > 500 mil from reference circuit.
If VREF feeds multiple ADCs: use individual RC filters at each ADC input (10 ohm + 1 uF).

16-bit SAR ADC (AD7689) reference design:

Reference: ADR4540B (4.096V, 5 uV RMS noise) placed 200 mil from ADC.

Decoupling: 10 uF X5R + 1 uF X7R + 100 nF C0G, all 0402, within 100 mil of VREF pin.

VREF trace: 15 mil wide, 150 mil long, with 8 mil guard traces, on L1 with solid L2 GND.

RC filter at ADC: 10 ohm (0402) + 4.7 uF (0402 X5R) provides 3.4 kHz LPF.

Total noise at ADC VREF pin: sqrt(5^2 + 1^2 + 2^2) = 5.5 uV RMS < 31 uV (0.5 LSB)

16-bit ADC VREF trace routed 2 inches on inner layer, passing under a 100 MHz FPGA I/O bus. No guard traces. Coupled noise from FPGA bus: 50 uV RMS (measured). Reference IC noise: 8 uV RMS. Total: sqrt(50^2 + 8^2) = 50.6 uV RMS. This exceeds 0.5 LSB (31 uV) and effectively reduces ADC to 15-bit performance.

Checkpoint 2.8.2: Analog Signal Guard Rings Major

Guard rings are copper structures that surround sensitive analog nodes to intercept leakage currents and capacitively coupled noise. They are essential for high-impedance nodes (op-amp inputs, sensor interfaces, electrometer circuits) where even picoamp leakage matters.

Guard Ring Design Principles

Surface leakage current:

I_leak = V_bias / R_surface

FR4 surface resistance: ~10^10 ohm (clean) to 10^8 ohm (contaminated)

At 3.3V bias: I_leak = 3.3V / 10^9 = 3.3 nA (with moisture/flux residue)

Effect on high-impedance node:

Op-amp with 10 Mohm feedback: 3.3 nA * 10 Mohm = 33 mV error!

Photodiode with 1 Gohm transimpedance: 3.3 nA is huge (signal may be pA)

Guard ring driven to same potential as protected node:

If guard is at same voltage as signal: no potential difference = no leakage between them

Leakage from supply rails goes to guard (low impedance) instead of signal node

Effective: reduces leakage by 100-1000x

Guard ring connections:

For op-amp non-inverting input: connect guard to output (follower topology = same voltage)

For inverting input: connect guard to non-inverting input (virtual ground)

For general protection: connect guard to local ground (intercepts leakage to ground)

Implementation Guidelines

Identify high-impedance nodes (>1 Mohm): op-amp inputs, sensor connections, bias networks.
Create a copper ring on ALL layers surrounding the sensitive node (top, inner, bottom).
Guard ring width: minimum 10 mil, preferred 20+ mil.
Guard ring gap to signal: 5-10 mil clearance (manufacturing minimum).
Guard ring gap to other copper: 10-20 mil clearance from power/signal traces.
Connect guard ring to appropriate potential (output for voltage follower, ground for general use).
No other traces should cross within the guard ring area - it must be a clean exclusion zone.

Electrometer-grade current measurement (fA-level):

TIA input node surrounded by guard ring on all 4 PCB layers.

Guard driven by op-amp output (feedback topology keeps guard at virtual ground).

No solder mask over guard ring area (solder mask can absorb moisture and increase leakage).

Guard ring extends 50 mil beyond the furthest sensitive trace.

Result: leakage current reduced from 2 nA (no guard) to 5 pA (with guard) at 85% RH.

High-impedance pH sensor input (10 Gohm source) with only a ground ring on the top layer. No guard on inner layers. A 3.3V power trace passes directly under the sensor input on L3. Surface leakage on the inner layer capacitively couples 3.3V switching noise to the sensor node, causing 50 mV of noise on what should be a 59 mV/pH signal.

Checkpoint 2.8.3: Quiet Ground Zones Major

Analog circuits require a "quiet" ground reference that is free from the high-frequency transients caused by digital switching. This is achieved through careful layout partitioning, NOT by splitting the ground plane.

Ground Noise Sources and Magnitude

Simultaneous Switching Noise (SSN) on ground:

V_bounce = N * L_via * dI/dt

Example: 32 FPGA pins switching simultaneously

N = 32, L_via = 1 nH, dI/dt = 10 mA / 500 ps = 20 MA/s

V_bounce = 32 * 1e-9 * 20e6 = 640 mV on local ground!

Ground plane voltage gradient:

Plane sheet resistance: Rs = rho / t = 1.7e-8 / (35e-6) = 0.5 mohm/square

For 1A return current over 1 inch (approximately 2 squares):

V_drop = 1A * 1 mohm = 1 mV (DC - usually acceptable)

But AC ground bounce from digital switching: 10-500 mV peak!

Strategy: Physical separation, not electrical isolation

Keep digital return currents AWAY from analog sense points.

Route digital signals so their return currents stay in the digital area.

Place analog components where no digital return currents flow beneath them.

Layout Zoning Strategy

Board Zoning (single solid ground plane on L2):

+--------------------------------------------------+
|  POWER SUPPLY      |        DIGITAL ZONE         |
|  (Switching)       |   (MCU, FPGA, Memory, I/O)  |
|  [Noisy Zone]      |   [Moderate Noise]          |
|                    |                              |
+--------------------+                              |
|                    |                              |
|  ANALOG ZONE       |                              |
|  (ADC, Sensor,     |   Return currents from       |
|   References)      |   digital section stay       |
|  [Quiet Zone]      |   in digital zone only       |
|                    |                              |
+--------------------------------------------------+
                     ^
                     |
          Domain boundary (routing discipline only)
          Ground plane is CONTINUOUS across boundary
          No digital signals cross into analog zone

Step-by-Step Implementation

Define board zones during floor planning: identify digital, analog, and power supply regions.
Place all analog sensitive components (ADC, references, sensors) in the quiet zone.
Place noisy components (SMPS, FPGA, clock generators) far from the quiet zone.
Route analog signals ONLY within the analog zone - never cross into digital area.
Route digital signals ONLY within the digital zone - never cross into analog area.
Interface between zones (SPI to ADC, etc.) should cross at one defined point with filtering.
Verify: no digital return currents flow under analog circuitry (check with current simulation).

Do NOT split the ground plane: A split ground forces return currents through a single connection point, creating a ground potential difference. A solid ground with layout discipline provides 20 dB better noise performance than a split ground in almost all practical designs.

Decoupling cap placement: Place digital IC decoupling caps on the DIGITAL side of the domain boundary. Return currents from digital ICs should complete their loop within the digital zone, never crossing into analog territory.

Checkpoint 2.8.4: Filter Pole Placement Major

Anti-aliasing filters before ADCs and reconstruction filters after DACs must be properly designed to prevent frequency content beyond the Nyquist frequency from corrupting the digitized signal. The filter cutoff, order, and component selection all affect PCB layout.

Anti-Aliasing Filter Design

Nyquist criterion:

f_sample >= 2 * f_max_signal (minimum)

Practical: f_sample >= 2.5 * f_max_signal (allows filter roll-off)

Required filter attenuation at f_sample/2:

Attenuation >= SNR_ADC + 6 dB (to prevent alias from degrading ADC performance)

For 16-bit ADC (96 dB SNR): need >102 dB at f_Nyquist

For 12-bit ADC (72 dB SNR): need >78 dB at f_Nyquist

Filter order determination:

Roll-off rate: N * 20 dB/decade (Butterworth) where N = filter order

Required order = attenuation / (20 * log10(f_alias / f_cutoff))

Example: 16-bit ADC, fs=1 MSPS, signal BW = 100 kHz:

f_Nyquist = 500 kHz, f_cutoff = 100 kHz (or slightly above)

Frequency ratio: 500/100 = 5 (0.7 decades)

Required attenuation: 102 dB

Order needed: 102 / (20 * 0.7) = 7.3 -> use 8th order Butterworth

Or: 4th order Butterworth with oversampling (fs = 10 MSPS, f_Nyquist = 5 MHz)

Then: 102 / (20 * log10(5000/100)) = 102 / 34 = 3 -> 3rd order sufficient with OS!

Component Selection for Filters

Component	Concern	Recommendation
Capacitors (filter)	Dielectric absorption, voltage coefficient	C0G/NP0 for precision (< 1 nF), X7R acceptable > 100 nF if not in signal path
Resistors (filter)	Noise (thermal), tolerance, TCR	Thin-film 0.1% for precision. Noise: 4kTRB = 41.38e-23300RBW
Op-amps (active filter)	GBW, slew rate, input noise	GBW > 10x filter frequency. Choose low-noise for input stage.
Inductors (LC filter)	DC resistance, saturation, self-resonance	Use only if Q control not critical. Air-core for precision.

PCB Layout for Filters

Place filter components in order of signal flow (input to output, left to right).
Keep filter components close together to minimize parasitic inductance between stages.
Ground all filter capacitor returns to the same ground point (star ground at filter).
Use ground pour under filter area for low-impedance returns.
Keep high-frequency signals away from filter components (especially high-Q inductors).
For multi-stage filters: shield between stages if gain > 40 dB (ground copper between).
Verify component self-resonance is above the stop-band frequency (especially C0G capacitors).

4th-order Butterworth anti-alias filter for 24-bit ADC (ADS1271, fs=105 kSPS):

Signal bandwidth: 20 kHz, Nyquist: 52.5 kHz

Filter: 4th-order Sallen-Key, fc = 25 kHz (Butterworth)

Components: 2x OPA1612 (low-noise op-amp, 1.1 nV/rtHz)

Capacitors: all C0G/NP0 (820 pF, 1.8 nF, 2.7 nF, 3.9 nF)

Resistors: 0.1% thin-film (2.2k, 4.7k values)

Layout: Components placed in signal flow order, ground pour underneath, 200 mil from digital.

Checkpoint 2.8.5: Noise Floor Analysis Major

The analog noise floor determines the minimum detectable signal. All noise sources (thermal, shot, flicker, coupled) must be quantified and summed to verify the system achieves required dynamic range.

Noise Source Calculations

Thermal noise (Johnson noise):

V_n = sqrt(4 * k * T * R * BW)

k = 1.38e-23 J/K, T = 300K (room temperature)

Example: R=10k ohm, BW=100 kHz:

V_n = sqrt(4*1.38e-23*300*10000*100000) = 4.07 uV RMS

Op-amp input voltage noise:

V_n_opamp = e_n * sqrt(BW) + (e_nf * sqrt(ln(f_H/f_L)))

Where: e_n = voltage noise density (nV/rtHz), e_nf = 1/f corner contribution

OPA1612: e_n = 1.1 nV/rtHz, f_corner = 3 Hz

At BW = 100 kHz: V_n = 1.1e-9 * sqrt(100e3) = 0.35 uV RMS

ADC quantization noise:

SNR_quant = 6.02*N + 1.76 dB (N = bits)

16-bit: SNR = 98 dB, noise floor = V_FS / (2^16 * sqrt(12)) = V_ref / 226,000

For 4.096V ref: quantization noise = 18.1 uV RMS (integrated over Nyquist BW)

Total system noise (RSS):

V_total = sqrt(V_thermal^2 + V_opamp^2 + V_coupled^2 + V_PS_noise^2)

SNR_system = 20*log10(V_signal_RMS / V_total)

SNR Budget Example: 16-bit Data Acquisition

System: 16-bit SAR ADC, 100 kSPS, 4.096V reference, 50 kHz signal bandwidth

Noise contributors:
  Source resistance (1k ohm):   V_n = sqrt(4*1.38e-23*300*1000*50000) = 0.91 uV
  Op-amp (OPA1612):            V_n = 1.1e-9 * sqrt(50000) = 0.246 uV
  Reference noise (ADR4540):    V_n = 5 uV RMS (wideband, filtered to 50 kHz: ~3 uV)
  ADC quantization noise:       V_n = 18.1 uV (inherent, cannot reduce)
  PCB coupled noise target:     V_n < 5 uV RMS (layout-dependent)
  Power supply noise (through PSRR): V_n = 10mV_ripple / 10^(80dB/20) = 1.0 uV

  Total: sqrt(0.91^2 + 0.246^2 + 3^2 + 18.1^2 + 5^2 + 1^2)
       = sqrt(0.83 + 0.06 + 9 + 327.6 + 25 + 1) = sqrt(363.5) = 19.1 uV RMS

  SNR = 20*log10((4.096/sqrt(2)) / (19.1e-6)) = 20*log10(151,600) = 103.6 dB
  Effective bits (ENOB) = (103.6 - 1.76) / 6.02 = 16.9 bits

  Result: ADC-limited (quantization noise dominates). Layout noise (5 uV) is insignificant.
  If PCB noise were 50 uV: total = sqrt(363.5 + 2500) = 53.5 uV, SNR = 94.4 dB, ENOB = 15.4
  50 uV of board noise would cost 1.5 bits of resolution!

Step-by-Step Noise Analysis

Identify all noise sources in the analog signal chain (resistors, active devices, references).
Calculate intrinsic noise for each source using formulas above.
Estimate PCB-coupled noise budget: allocate < 30% of total noise to layout effects.
Calculate total noise using RSS summation.
Verify SNR meets system requirement (e.g., datasheet ENOB - 0.5 bits for layout margin).
If PCB noise dominates: improve layout (more shielding, better routing, quieter ground).
Measure actual noise after board fabrication and compare to calculated budget.

Checkpoint 2.8.6: Analog/Digital Boundary Management Critical

The interface between analog and digital domains is the most critical area in a mixed-signal design. Signals crossing this boundary can carry digital noise into the analog domain or allow analog ground bounce to affect digital timing.

Boundary Crossing Strategies

Signal types that cross the analog/digital boundary:
  1. ADC digital output (SPI/I2C/Parallel) - digital signal from analog IC
  2. DAC digital input (SPI/I2C/Parallel) - digital signal to analog IC
  3. Clock signals to ADC/DAC - digital clock affecting analog sample point
  4. Control signals (chip select, reset) - digital control of analog functions
  5. Mixed-signal IC power (AVDD, DVDD pins on same IC)

Boundary crossing rules:
  - Cross at ONE defined location (not scattered around the board)
  - Use the shortest possible crossing path
  - Filter clock signals at the boundary (series resistor + bypass cap)
  - Digital outputs from ADC: route directly into digital zone (don't linger in analog zone)
  - Place mixed-signal ICs AT the boundary (analog pins facing analog zone, digital pins facing digital)

Mixed-Signal IC Placement and Connections

ADC/DAC with separate AVDD and DVDD pins:

AVDD: connected to clean analog supply (LDO, heavy filtering)

DVDD: can often be powered from same supply with local ferrite bead isolation

AGND and DGND pins: BOTH connect to the same solid ground plane

Never leave DGND floating or connected through a resistor!

Decoupling strategy for mixed-signal ICs:

AVDD decoupling: 10 uF + 100 nF (C0G if possible), placed on ANALOG side

DVDD decoupling: 10 uF + 100 nF (X7R acceptable), placed on DIGITAL side

Key: return currents from AVDD caps stay in analog zone

Return currents from DVDD caps stay in digital zone

Power supply filtering between domains:

Option 1: Ferrite bead (BLM15AG601SN1, 600 ohm at 100 MHz) + 10 uF cap

Creates pi-filter: provides >40 dB isolation above 10 MHz

Option 2: Dedicated LDO for analog supply (TPS7A47xx series, ultra-low noise)

PSRR >60 dB at 1 MHz, output noise <10 uV RMS

Step-by-Step Verification

Identify ALL signals that cross between analog and digital domains.
Verify mixed-signal ICs are placed at the domain boundary with correct pin orientation.
Check that AGND and DGND pins both connect to the common ground plane (no isolation).
Verify digital output traces from ADCs route directly into the digital zone (no loops in analog).
Check power supply isolation: ferrite beads or separate LDOs between digital and analog supplies.
Verify decoupling capacitor placement: AVDD caps on analog side, DVDD caps on digital side.
Ensure clock to ADC/DAC is filtered at the boundary (series R + shunt C for edge rate reduction).

ADS8688 (16-bit, 8-ch SAR ADC) placement:

ADC placed at analog/digital boundary. Analog input pins face left (analog zone). SPI + digital pins face right (digital zone). AVDD (5V): powered by TPS7A4901 LDO in analog zone with 10uF+100nF C0G decoupling. DVDD (3.3V): powered from main 3.3V through BLM15AG601 ferrite + 10uF+100nF local decoupling on digital side. AGND and DGND: both pins soldered directly to continuous ground plane (L2). No ground split. SPI clock filtered with 33 ohm series + 22 pF shunt at the boundary crossing.

Designer splits the ground plane between "AGND" and "DGND" and connects them with a 0-ohm resistor under the ADC. The DGND decoupling cap return current must flow through the 0-ohm link to reach the DVDD supply return. This 0-ohm has 0.5 nH inductance. At 100 MHz switching: V = L*dI/dt = 0.5e-9 * 50e-3/1e-9 = 25 mV ground bounce between domains. This 25 mV appears as common-mode noise on the ADC, degrading SNR by 6 dB (1 bit of resolution lost).

LTspice: Simulate the power supply filtering network (ferrite + capacitor) to verify attenuation at digital switching frequencies. Model ferrite with manufacturer's S-parameter data (available from Murata SimSurfing).

Cadence Sigrity PowerSI: Run power integrity simulation to visualize ground current flow patterns. Verify that digital switching currents do not flow under analog circuitry.

Oscilloscope verification: After board fabrication, measure noise at ADC VREF and analog supply pins using a differential probe. Compare to budget. If noise exceeds budget, use near-field probe to identify the coupling source.