Module 3.3 - Power & Ground Planes

Checkpoint 1: Plane Pairs Closely Coupled (< 4mil Dielectric) Critical

A closely-spaced power/ground plane pair acts as a distributed capacitor across the entire board area. This plane capacitance provides high-frequency decoupling (above 500MHz) that discrete capacitors cannot achieve due to their mounting inductance. The closer the planes, the higher the capacitance per unit area and the lower the spreading inductance.

Plane Capacitance Formula

Spreading Inductance vs. Dielectric Thickness

Stackup Design for Optimal PI

1. Place primary power/ground plane pair on adjacent inner layers with thinnest possible dielectric (2-4 mil prepreg).
2. For multi-power-rail designs, dedicate the tightest plane pair to the lowest-impedance supply (typically VCCINT/FPGA core).
3. Maintain symmetry in stackup to prevent board warpage during lamination.
4. Use high-Dk dielectric materials (Dk > 4) between plane pairs for maximum capacitance.
5. Verify with your fabricator that the specified thin dielectric is achievable and repeatable.

Example Stackup (12-layer FPGA board)

Layer  Type      Material         Thickness   Purpose
--------------------------------------------------------------
L1     Signal    Copper 1oz       1.2 mil     Top components/routing
       Prepreg   FR4 2116         4.0 mil
L2     Power     Copper 1oz       1.2 mil     VCCINT (0.85V)
       Core      FR4              2.0 mil     ** TIGHT COUPLING **
L3     Ground    Copper 1oz       1.2 mil     GND (primary reference)
       Prepreg   FR4 1080         3.0 mil
L4     Signal    Copper 0.5oz     0.6 mil     High-speed routing
       Core      FR4              8.0 mil
L5     Signal    Copper 0.5oz     0.6 mil     General routing
       Prepreg   FR4 2116         4.0 mil
L6     Power     Copper 1oz       1.2 mil     3.3V
       Core      FR4              3.0 mil     ** COUPLED **
L7     Ground    Copper 1oz       1.2 mil     GND (secondary)
       Prepreg   FR4 2116         4.0 mil
L8     Signal    Copper 0.5oz     0.6 mil     General routing
       Core      FR4              8.0 mil
L9     Signal    Copper 0.5oz     0.6 mil     High-speed routing
       Prepreg   FR4 1080         3.0 mil
L10    Ground    Copper 1oz       1.2 mil     GND (tertiary)
       Core      FR4              2.0 mil     ** TIGHT COUPLING **
L11    Power     Copper 1oz       1.2 mil     1.8V
       Prepreg   FR4 2116         4.0 mil
L12    Signal    Copper 1oz       1.2 mil     Bottom components/routing
--------------------------------------------------------------
Total thickness: ~62 mil (1.57 mm)
            

Checkpoint 2: No Unnecessary Plane Splits Critical

Every split (gap, cutout, or void) in a power or ground plane creates an impedance discontinuity, increases current path length, reduces plane capacitance, and can create a slot antenna that radiates EMI. Plane splits should only exist where electrically necessary (different voltage domains) and never as an artifact of careless routing.

Impact of Plane Splits

How to Check for Plane Splits

1. In PCB layout tool, view each power/ground plane layer individually.
2. Look for any gaps, channels, or narrow necks in the copper pour.
3. Check for routing channels that cut through planes (common in auto-routed boards).
4. Verify no thermal relief spokes create effective splits between plane regions.
5. Check via fields (BGA areas) -- dense via patterns can create Swiss cheese effect that fragments the plane.
6. Use DRC/connectivity check to verify all plane regions are electrically connected.

Acceptable vs. Unacceptable Splits

Checkpoint 3: Split Planes with Stitching Capacitors Major

When plane splits are necessary (different voltage domains, analog/digital separation), stitching capacitors provide a low-impedance AC path across the split at high frequencies. This maintains signal return path continuity and reduces EMI radiation from the slot.

Stitching Capacitor Selection

Placement Rules

1. Place stitching caps across the split at regular intervals (every 5-10mm for GHz designs).
2. Always place a stitching cap at each point where a signal trace crosses the split.
3. Place caps as close to the split as possible (within 1mm of the gap edge).
4. Use 100nF X7R 0402 as standard stitching cap value (good from 1MHz to 100MHz).
5. For GHz applications, add parallel 1nF C0G caps for extended high-frequency coverage.
6. Connect capacitor ground pads to respective planes with short, low-inductance paths (via-in-pad preferred).

Checkpoint 4: Current Density Uniform Major

Non-uniform current density in power planes creates localized heating (hot spots), increased voltage drop, and potential reliability issues. Current tends to crowd at narrow necks, sharp corners, and near via clusters. Simulation is the only reliable way to verify current density distribution.

Current Density Limits

How to Identify Hot Spots

1. Run DC IR-drop simulation (Sigrity PowerDC or SIwave DCIR) with maximum load currents.
2. Examine current density map -- look for red/yellow regions indicating high density.
3. Identify bottlenecks: narrow plane sections, connector areas, via clusters.
4. Check current density at all plane necks (areas where width is constrained by cutouts or other nets).
5. Verify temperature rise at hot spots is within board material limits (FR4: +50C max over ambient).
6. Widen narrow sections or add copper relief to reduce current crowding.

Checkpoint 5: Plane Resonance Above Operating Frequency Major

Power/ground plane pairs behave as resonant cavities at frequencies where the board dimensions are multiples of the half-wavelength. At these resonant frequencies, the plane impedance shows sharp peaks that can amplify power supply noise and cause EMI radiation at board edges.

Plane Resonance Frequency Calculation

Resonance Mitigation Strategies

• Ensure first resonance is above f_knee: If f_10 > f_knee of your fastest signal, plane resonance is less critical.
• Decoupling capacitors at resonant voltage maxima: Place HF caps at the locations where resonant modes have voltage peaks (board edges and center for f_10, f_01).
• 20H rule (deprecated but useful concept): Pull back power plane edges 20x the dielectric height from board edge to reduce edge radiation. Example: 4mil dielectric -> pull back 80 mils (2mm).
• Embedded capacitance material: High-Dk thin laminates (e.g., 3M C-Ply, Sanmina ZBC) provide extreme capacitance that damps resonances.
• Lossy plane pair: Some advanced materials add controlled loss to damp resonant peaks.
• Via stitching at board edges: Dense ground via fencing (every 3mm) along board perimeter reduces edge radiation at resonance.

Checkpoint 6: Adequate Copper Weight for Current Critical

Copper planes must carry the required current without excessive temperature rise. IPC-2152 provides the standard methodology for determining required copper area (width x thickness) based on current, acceptable temperature rise, and whether the conductor is internal or external.

IPC-2152 Current Capacity Calculation

Copper Weight Selection Guide

Values assume 20C temperature rise above ambient, FR4 substrate. Conservative; verify with IPC-2152 charts or simulation.