Checkpoint 1: Load Step Response Within Specification Critical
The load step response characterizes how the power delivery system (VRM + PDN + decoupling) responds to sudden changes in current demand. This is the most important dynamic characteristic because it determines whether the supply voltage stays within the IC's operating range during real-world switching activity.
Load Step Response Analysis
Time-domain response to a current step (dI in time dt):
Phase 1: Initial ESL spike (first 1-10ns)
V_spike = L_total * dI/dt
L_total = ESL_cap_mount + L_via + L_trace
Example: L=1nH, dI=10A, dt=1ns: V_spike = 1e-9*10/1e-9 = 10V (clamped by cap)
Practical: V_spike = 1nH * 10A/5ns = 2V peak (before cap responds)
Phase 2: Capacitor discharge (10ns - 10us)
V_droop = dI * ESR + dI * t / C_local
ESR = equivalent series resistance of decoupling caps
C_local = total local decoupling capacitance
Example: dI=10A, ESR=1mOhm, t=1us, C=200uF:
V_droop = 10*0.001 + 10*1e-6/200e-6 = 10mV + 50mV = 60mV
Phase 3: VRM response (10us - 1ms)
V_recovery determined by VRM bandwidth and gain
Time to recover = ~3-5 * (1/f_BW)
Example: f_BW = 100kHz, recovery time = 30-50us
Step-by-Step Measurement Procedure
- Equipment setup: Oscilloscope (500MHz+), active differential probe (or tip-and-barrel), electronic load with fast transient mode (slew > 5A/us).
- Probe connection: Solder probe tip directly to IC power pin (or nearest via). Use minimal ground loop (solder ground barrel to adjacent GND via). Never use 6-inch ground clip!
- Load configuration: Set electronic load for step from 10% to 90% of rated current. Set minimum transition time (typically < 1us).
- Trigger: Trigger on load current sense signal (or use external trigger from load sync output).
- Capture: Set timebase to capture full transient including recovery (typically 50-100us/div). Use averaging OFF (single-shot) for first look.
- Measure: Use cursors to measure: peak undershoot, peak overshoot, recovery time to within 1% of nominal, ringing frequency if present.
- Validate: Compare measured values against IC specification. Repeat at temperature extremes.
Interpreting Scope Captures
Healthy response characteristics:
- Clean single undershoot/overshoot (no ringing)
- Peak excursion within voltage tolerance band
- Recovery in < 50us for fast regulators
- No oscillation or instability after settling
Warning signs in scope captures:
- Multiple ringing cycles: Phase margin too low (< 45 deg)
- Slow exponential recovery: Bandwidth too low
- Staircase response: VRM hitting current limit during step
- High-frequency oscillation superimposed: May be loop instability or EMI pickup
- Different response at different loads: Gain variation (pole/zero shift with load)
Excellent load step response (1.0V FPGA core, 0-15A step):
Measured with Keysight MSOX6004A + N7020A power rail probe:
- Load step: 0A to 15A in 200ns (75 A/us slew)
- Peak undershoot: 42mV (4.2% of 1.0V -- within 5% spec)
- Time to peak: 2.5us (consistent with 200kHz BW regulator)
- Recovery to +/-1%: 18us
- Overshoot on release (15A to 0A): 38mV (3.8%)
- No visible ringing (single excursion -- PM > 55 degrees indicated)
- Consistent results at -40C, +25C, and +85C
Failing response with excessive undershoot:
1.8V I/O rail, 0-3A step, TPS62130:
- Peak undershoot: 250mV (13.9% of 1.8V -- exceeds 5% spec!)
- Three cycles of ringing at 35kHz before settling
- Recovery time: 120us (spec: < 50us)
Root cause analysis:
- Output capacitor: Only 10uF (datasheet minimum, but insufficient for this load step)
- Phase margin measured at 28 degrees (too low -- explains ringing)
Fix: Add 22uF output cap (total 32uF), adjust compensation for PM = 55 deg.
Keysight N7020A Power Rail Probe: Specifically designed for power integrity. 2GHz BW, 1:1 attenuation, +/-24V range. Use for all PI measurements.
Picotest J2111A Current Injector: Precision current step generator for controlled transient testing. Better repeatability than electronic loads for small steps.
Tip: Always measure at the IC, not at the regulator output. The PDN between regulator and IC adds impedance that affects the real voltage the IC sees.
Checkpoint 2: Voltage Droop Less Than Allowed Ripple Critical
Voltage droop is the transient voltage reduction that occurs when load current suddenly increases. The total voltage droop budget must account for: DC IR drop (steady-state), AC droop from transient current steps, and high-frequency ripple from switching. All three combined must remain within the IC's voltage tolerance window.
Voltage Budget Allocation
Total voltage tolerance budget (example: 1.0V +/-5% = 50mV total):
V_nominal = 1.000V
V_min = 0.950V (absolute minimum for IC operation)
V_max = 1.050V (absolute maximum)
Budget allocation:
1. Regulator accuracy: +/-1% = +/-10mV (from V_ref + resistor tolerance)
2. DC IR drop (VRM to IC): -8mV (from plane/trace resistance * I_avg)
3. Transient droop (load step): -25mV (from PDN impedance * dI)
4. Switching ripple: +/-5mV (from output ripple of buck converter)
5. Temperature variation: +/-2mV (from component drift)
Worst case low: 1000 - 10 - 8 - 25 - 5 - 2 = 950mV (exactly at limit!)
Need margin: Set nominal to 1.010V to provide 10mV safety margin.
Droop Mitigation Strategies
- Reduce PDN impedance: Lower Z_target means less droop for same current step. Add more capacitors or use lower-ESL mounting.
- Increase VRM bandwidth: Faster VRM response reduces the duration of droop (capacitors discharge less before VRM corrects).
- Adaptive Voltage Positioning (AVP): Set output voltage higher at no-load so droop at full-load stays within window. Also called "load-line" control.
- Reduce DC IR drop: Use wider traces/planes, heavier copper, or move VRM closer to load.
- Current spreading: Distribute current draw across more pins/vias to reduce localized droop.
Adaptive Voltage Positioning (Load-Line) Design
AVP concept:
V_out = V_target - R_loadline * I_out
Where R_loadline = Target impedance (flat from DC to crossover)
Without AVP: V_out(no load) = V_out(full load) = V_target
Droop goes from V_target downward -- uses only half the tolerance band.
With AVP: V_out(no load) = V_target + R_LL * I_max/2
V_out(full load) = V_target - R_LL * I_max/2
Droop is centered in tolerance band -- effectively doubles available droop budget!
Example: V_target = 1.0V, tolerance = +/-50mV, I_max = 20A
Without AVP: Available droop = 50mV
With AVP: R_LL = 100mV / 20A = 5 mOhm
V_out(no load) = 1.050V, V_out(full load) = 0.950V
Available droop budget = 100mV (2x improvement!)
Droop well within budget with AVP:
FPGA VCCINT: 0.85V +/-5% (42.5mV tolerance each side)
AVP implemented: R_loadline = 2 mOhm
At no load: V_out = 0.87V
At 20A full load: V_out = 0.85V - 20*0.002 = 0.81V... wait, that exceeds -5%!
Correct: V_out(no load) = 0.85V + 10A*0.002 = 0.87V (centered for 10A average)
Transient from 10A to 20A: droop = 10A * Z_PDN = 10A * 2mOhm = 20mV
V_min = 0.87V - 20A*0.002 = 0.83V (within 0.808V minimum -- OK with margin)
Droop exceeds budget, causing bit errors:
DDR4 VDD = 1.2V, tolerance = +/-3% = +/-36mV
DC IR drop: 15mV (long trace from regulator to memory)
Transient droop: 45mV (insufficient decoupling near memory ICs)
Ripple: 8mV
Total worst-case: 15 + 45 + 8 = 68mV below nominal!
V_min = 1.2V - 0.068V = 1.132V (below 1.164V minimum!)
Result: DDR4 write training fails at 2400MT/s. Works unreliably at 2133MT/s.
Checkpoint 3: Recovery Time Acceptable Major
Recovery time is measured from the onset of a load transient to when the output voltage returns to and remains within the steady-state regulation band (typically +/-1% of nominal). Long recovery times indicate the VRM loop is too slow or the output capacitance is insufficient to support the load during the VRM response period.
Recovery Time Estimation
Approximate recovery time:
t_recovery = 3 to 5 * (1 / f_crossover)
Where f_crossover = control loop 0dB crossover frequency
For TPS62130 (f_c = 180kHz):
t_recovery = 4 / 180e3 = 22us (approximate)
For TPS54331 (f_c = 70kHz):
t_recovery = 4 / 70e3 = 57us
Factors that extend recovery time:
- Low phase margin: Ringing adds settling time (t = 5-10 / f_c for PM < 40 deg)
- Current limiting: If step exceeds OCP, recovery is very slow (hiccup mode)
- Inductor saturation: If peak current saturates inductor, recovery is erratic
- Large output capacitance: More capacitor slows the VRM response
Typical specifications:
- FPGA core: < 50us recovery time
- DDR memory: < 100us
- General I/O: < 200us
Improving Recovery Time
- Increase VRM bandwidth: Higher crossover frequency means faster response. But limited by switching frequency (max f_c = f_sw/5).
- Optimize compensation: Maximize phase margin at higher crossover frequency. Use Type III compensation if needed.
- Reduce output capacitance: Less capacitance means faster VRM response (but increases droop -- tradeoff).
- Use higher switching frequency regulator: Higher f_sw allows higher f_c. TPS62130 at 2.5MHz allows BW up to 500kHz.
- Multi-phase VRM: Interleaved phases respond faster than single-phase at equivalent ripple.
Fast recovery meeting specification:
FPGA core supply (1.0V, 20A max), requirement: recovery < 50us
VRM: ISL8225M 20A multi-phase buck, f_sw = 600kHz/phase, f_c = 200kHz
Measured recovery: 18us from peak droop to within +/-1% band
Phase margin: 62 degrees (clean single-pulse response, no ringing)
Works consistently across -40C to +85C temperature range.
Slow recovery causing system timing violation:
Processor core supply (1.1V), recovery measured: 250us
Problem: Processor enters turbo mode, demands current, voltage droops 60mV.
Takes 250us to recover. During this time, processor operates at 1.04V.
Processor frequency at 1.04V is not guaranteed (spec requires 1.05V for turbo clock).
Result: Intermittent computation errors during burst workloads.
Root cause: VRM bandwidth only 15kHz due to incorrect compensation.
Checkpoint 4: Overshoot Within Vmax Critical
Overshoot occurs when load current suddenly decreases (load release). The inductor current cannot change instantaneously, so excess energy flows into the output capacitor, raising the voltage. If the overshoot exceeds the IC's absolute maximum supply voltage, permanent damage can occur.
Overshoot Estimation
Initial overshoot (before VRM responds):
V_overshoot = dI * ESR + (1/2 * L_inductor * dI^2) / (C_out * V_out)
First term: ESR step (instantaneous)
Second term: Energy stored in inductor transferred to capacitor
Example: TPS54331, V_out=3.3V, L=10uH, C_out=94uF, dI=3A (full to no-load):
V_overshoot_ESR = 3 * 3mOhm = 9mV
V_overshoot_LC = (0.5 * 10e-6 * 9) / (94e-6 * 3.3) = 45e-6/310e-6 = 145mV
Total overshoot: ~154mV above nominal (4.7% -- check Vmax!)
If V_max = 3.3V * 1.05 = 3.465V: Overshoot to 3.454V -- BARELY within spec!
For modern regulators with fast response:
Practical overshoot is typically 50-70% of the calculated value
(VRM responds within 1-2us, before full LC energy transfer occurs)
Overshoot Reduction Techniques
- Output voltage clamp (TVS diode): Place a TVS diode across the output to clamp overshoot. Select V_clamp between V_max and V_nominal. Example: For 3.3V rail with 3.63V max, use SMAJ3.3A (clamps at 3.6V).
- Increase output capacitance: More C absorbs inductor energy with less voltage rise. V_overshoot proportional to 1/C.
- Reduce inductor value: Less inductance means less stored energy during load release. But increases ripple current.
- Active clamp circuit: MOSFET clamp activated when voltage exceeds threshold. Dissipates excess energy.
- Faster VRM response: Higher bandwidth means the VRM reduces duty cycle faster, limiting energy delivery.
Overshoot within safe limits:
1.8V rail (max 1.89V per IC spec), load release: 5A to 0A
Regulator: TPS62130, L=2.2uH, C_out=44uF
Calculated: V_os = 5*2mOhm + (0.5*2.2e-6*25)/(44e-6*1.8) = 10mV + 347mV
Seems excessive, but actual measured overshoot: 65mV (regulator responds in 3us)
V_peak = 1.865V (within 1.89V max -- 25mV margin)
Overshoot exceeding absolute maximum:
1.0V FPGA core (V_max_abs = 1.1V), load release: 20A to 2A
VRM with slow response (BW = 30kHz): Does not respond for 30us
During 30us: Inductor delivers excess current to caps
V_overshoot measured: 150mV above 1.0V = 1.15V peak!
This exceeds absolute maximum of 1.1V by 50mV!
Result: Gradual oxide degradation. FPGA fails after 6 months in the field.
Fix: Add TVS clamp + increase VRM bandwidth + add output capacitance.
- Checking overshoot only at room temperature: At cold temperatures, ESR increases and VRM may be slower. Test at -40C for worst-case overshoot.
- Ignoring absolute maximum ratings: The 5% tolerance band is for OPERATION. Absolute maximum may be 10% -- but exceeding it even briefly causes reliability degradation.
- Not testing full load release: The worst overshoot occurs at full-load-to-no-load transition, not at partial load changes.
Checkpoint 5: PSRR Adequate at Operating Frequency Major
Power Supply Rejection Ratio (PSRR) measures how well a voltage regulator attenuates noise on its input supply from appearing on its output. For sensitive analog circuits (ADCs, PLLs, oscillators, RF front-ends), high PSRR at the operating frequency is essential to prevent supply noise from degrading performance.
PSRR Definition and Calculation
PSRR = 20 * log10(V_noise_input / V_noise_output) [in dB]
Or equivalently: V_noise_output = V_noise_input / 10^(PSRR/20)
PSRR is frequency-dependent:
- At DC: PSRR = Open-loop gain of regulator (typically 60-80 dB for LDOs)
- At f < f_BW: PSRR = Loop gain (decreases at -20dB/decade above dominant pole)
- At f > f_BW: PSRR = Feedforward attenuation (may be 0-20dB for LDOs)
- At very high f: PSRR determined by capacitor divider (input cap / output cap)
Example: TPS7A4901 LDO PSRR:
At 100 Hz: 72 dB
At 10 kHz: 65 dB
At 100 kHz: 52 dB
At 1 MHz: 38 dB
At 10 MHz: 20 dB
If input has 100mV switching noise at 500kHz:
PSRR at 500kHz = ~45 dB
V_noise_out = 100mV / 10^(45/20) = 100mV / 177.8 = 0.56mV on output
PSRR Requirements by Application
| Application |
Frequency of Concern |
PSRR Required |
Recommended Regulator |
| ADC reference voltage |
Sampling frequency (1-100 MHz) |
> 50 dB |
TPS7A47 + ferrite bead filter |
| PLL/Clock supply |
VCO frequency (100MHz-5GHz) |
> 40 dB |
Ultra-low-noise LDO (LP5907) |
| RF transceiver |
Carrier frequency (700MHz-6GHz) |
> 60 dB |
Cascaded LDO + LC filter |
| SerDes/Transceiver PLL |
Jitter-sensitive (1-100 MHz) |
> 45 dB |
TPS7A87/7A88 series |
Enhancing PSRR with External Filtering
Cascaded filter approach:
Stage 1: Ferrite bead + capacitor (LC filter)
Ferrite: BLM18PG221SN1D (220 ohm at 100MHz)
Cap: 10uF MLCC
Filter corner: f_c = 1/(2*pi*sqrt(L_bead*C)) at low frequency
At 100MHz: Attenuation = Z_bead/(Z_bead + Z_cap) = 220/(220+0.016) = ~0dB
Wait -- ferrite is resistive at 100MHz, so it dissipates noise:
V_attenuation = Z_cap / (Z_bead + Z_cap) = 0.016/220.016 = -82dB!
Stage 2: LDO (adds additional 30-50dB at frequency of interest)
Total PSRR: Filter_attenuation + LDO_PSRR
At 100MHz: 82dB + 20dB = 102dB total rejection
100mV input noise becomes: 100mV / 10^(102/20) = 0.79 uV on output (exceptional!)
High-PSRR supply for 14-bit ADC (ADS4249):
ADC AVDD requirement: < 10uVrms noise at sampling frequency (250 MSPS)
Supply chain: 5V Buck (TPS54331) -> Ferrite + Cap filter -> LDO (TPS7A4901) -> ADC
Buck output noise at 570kHz fundamental: 30mV pp
Ferrite (BLM15AG601) attenuation at 570kHz: 12dB
LDO PSRR at 570kHz: 42dB
Total rejection: 54dB
Noise at ADC: 30mV / 10^(54/20) = 30mV / 501 = 60uV pp = ~10uVrms (meets spec!)
Buck converter directly powering PLL (jitter issue):
Clock PLL (Si5345) powered directly from TPS62130 buck output (no LDO filter).
Buck ripple at 2.5MHz: 5mV pp
PSRR of "buck to PLL supply" path: 0dB (no additional filtering!)
PLL supply noise sensitivity: 1ps jitter per mV supply noise (from Si5345 datasheet)
Jitter contribution: 5mV * 1ps/mV = 5ps pp supply-induced jitter
Budget: Total jitter must be < 1ps rms for 10G Ethernet.
5ps pp supply noise alone exceeds budget!
Fix: Add LDO (LP5907) between buck and PLL. Reduces noise by 40dB.
Checkpoint 6: Noise Spectrum Characterized Minor
Beyond simple ripple voltage measurement, a complete noise spectrum characterization identifies all noise components on a power rail: switching fundamental and harmonics, broadband noise floor, narrowband spurs from digital activity, and low-frequency (1/f) noise. This spectral view reveals issues that time-domain measurements alone may miss.
Noise Measurement Methodology
- Time domain: Capture output voltage with AC-coupled oscilloscope (20MHz BW limit for ripple, full BW for HF noise). Measure pk-pk and RMS.
- FFT analysis: Use oscilloscope FFT or spectrum analyzer. Set span to cover DC to 10x switching frequency. Resolution bandwidth: 1-10 kHz.
- Low-frequency noise: Use spectrum analyzer from 10Hz to 100kHz to capture 1/f noise, regulator limit cycling, and audio-frequency components.
- Identify spectral components: Switching fundamental (f_sw), harmonics (2*f_sw, 3*f_sw...), clock-related spurs, broadband noise floor.
- Compare to sensitivity: Overlay IC noise sensitivity curve (jitter-to-noise transfer function for PLLs, ENOB degradation for ADCs).
- Document: Record complete noise spectrum for each rail. This becomes the baseline for future debugging.
Noise Budget Spreadsheet Approach
Example noise budget for 1.0V FPGA core:
Frequency | Source | Level | Impact
---------------------------------------------------------
DC | IR drop | -8mV | Reduces voltage margin
1kHz | VRM noise | 0.1mV | Negligible
570kHz | Buck switching | 3mV pp | Within spec (< 10mV)
1.14MHz | 2nd harmonic | 1.5mV | Within spec
1.71MHz | 3rd harmonic | 0.8mV | Within spec
100MHz | Digital switching| 5mV pp | Affects clock jitter
500MHz | SerDes toggle | 2mV pp | Affects SerDes BER
---------------------------------------------------------
Total RMS noise (integrated 10Hz-1GHz): 4.2 mVrms
Specification: < 10 mVrms
Status: PASS with 7.6dB margin
Comprehensive noise characterization documentation:
Rail: VCC_PLL (1.8V, low-noise LDO output)
Measurement: Spectrum analyzer (R&S FSV3007), probe: N7020A
Results:
- Switching spur at 2.5MHz: -92 dBV (25uV) -- well filtered
- Broadband floor (1-100MHz): -110 dBV/sqrt(Hz) = 3.16 uV/sqrt(Hz)
- Integrated noise (10Hz-100MHz): 18 uVrms
- No unexpected spurs or narrowband interference
- PLL jitter with this supply: 0.3ps rms (meets 1ps budget with margin)
Unexpected spur causing interference:
VCC_ADC (3.3V) shows unexpected spur at 48MHz (-65 dBV = 560uV).
This frequency is the MCU core clock (48MHz).
MCU ground bounce couples through shared power plane into ADC supply.
Effect: ADC output shows fixed-pattern noise at exactly 48MHz modulation.
SNR degradation: 3dB (from 72dB to 69dB SINAD).
Fix: Split analog/digital ground at ADC, add ferrite bead isolation on AVDD supply.
Measurement Tips:
- Use AC coupling on scope to see small signals on DC rails (100mV/div or less).
- 20MHz bandwidth limit shows switching ripple cleanly without HF noise obscuring.
- Full bandwidth (500MHz+) shows actual HF noise the IC experiences.
- Ground spring tip or solder-in probe gives 10-20dB better noise floor than clip lead.
Spectrum Analyzer Settings:
- Start: 10 kHz, Stop: 1 GHz (for general characterization)
- RBW: 1-10 kHz (tradeoff between speed and frequency resolution)
- Detector: RMS (for noise floor) or Peak Hold (for worst-case spurs)
