Tutorial 5.4: Via Strategy

Introduction to Via Strategy

Vias are the vertical interconnects that link PCB layers together. Their design impacts signal integrity, power delivery, thermal management, and manufacturing cost. A well-planned via strategy considers the electrical requirements, manufacturing process, reliability, and cost trade-offs.

Via Type Overview

Checkpoint: Via Types Defined (Through/Blind/Buried/Micro)

Via Selection Decision Tree

START: Does the connection need to span all layers?
  |
  +-- YES --> Use Through-Hole Via
  |             Standard: 0.3mm drill, 0.6mm pad
  |             Large:    0.4mm drill, 0.8mm pad
  |
  +-- NO  --> Is it from an outer layer to an inner layer?
                |
                +-- YES --> Is the board HDI / fine-pitch (<=0.65mm)?
                |             |
                |             +-- YES --> Use Microvia (laser, 0.1mm drill, 0.25mm pad)
                |             |
                |             +-- NO  --> Use Blind Via (mech drill, 0.2mm drill, 0.45mm pad)
                |
                +-- NO  --> (Inner to Inner)
                              Use Buried Via (requires sequential lamination)
                              Consider: Can through-via achieve the same with route restructuring?
            

Manufacturer Via Capabilities

Aspect Ratio Limits

The aspect ratio (board thickness : drill diameter) determines drilling reliability:

Checkpoint: Via-in-Pad Usage Rules

When to Use Via-in-Pad

• BGA pitch <= 0.65mm: Insufficient space for dog-bone fan-out between pads
• QFN/DFN thermal pads: Thermal vias in the exposed pad for heat transfer to inner layers/bottom
• BGA thermal pads: Center ground/thermal pads on large BGAs
• High-frequency RF: Eliminate via stub for through-hole vias (alternative to back-drill)
• Ultra-compact designs: Mobile/wearable where every mm2 matters

Via-in-Pad Fill Types (IPC-4761)

Checkpoint: Via Current Rating Verified

Via Current Capacity Calculation

Via current capacity depends on the plated barrel cross-section:

Cross-section area = pi * ((D/2)^2 - ((D-2T)/2)^2)
                   = pi * T * (D - T)

Where:
  D = Finished hole diameter
  T = Plating thickness (typically 1 mil / 25um minimum per IPC-6012 Class 2)

Example: 0.3mm drill, 25um (1mil) plating
  Area = pi * 0.025 * (0.3 - 0.025) = 0.0216 mm2

Current capacity (10C rise, 1.6mm board): approximately 0.5A per via

For 20C rise: approximately 0.7A per via
For 30C rise: approximately 1.0A per via
            

Via Current Rating Table

Power Via Array Sizing

For high-current connections (regulator output, battery connections, motor drives):

1. Determine maximum DC current + transient peak
2. Select via size based on manufacturing preference (typically 0.3-0.4mm)
3. Calculate number of vias needed: N = I_max / I_per_via (with 50% derating)
4. Arrange vias in array pattern under power pads or along power traces
5. Example: 3A supply needs 3 / (0.5 * 0.5) = 12 vias (0.3mm, derated 50%)

Checkpoint: Anti-Pad Clearance Adequate

Anti-Pad Sizing Rules

Non-Functional Pad Removal

Non-functional pads (NFPs) are via pads on layers where no connection is made. Removing them:

• Restores plane copper, improving power/ground continuity
• Opens routing channels between vias on inner signal layers
• Reduces parasitic capacitance (minor impact for most designs)
• Required for HDI designs with tight via-to-via spacing

Checkpoint: Via Stitching for Ground Continuity

Via Stitching Spacing Guidelines

Via Stitching Applications

1. Ground plane connection: Regular grid of vias across the board connecting all GND layers (typically 20-50mm spacing for general use)
2. Shield fence: Tight row of vias along the perimeter of sensitive areas (spacing = 2x via pad diameter for effective shield)
3. Board edge grounding: Row of vias along board edge connecting top/bottom ground pour to prevent edge radiation
4. Split plane bridging: Vias connecting ground regions across routing channels
5. Return path vias: GND vias adjacent to every signal via transition (different from blanket stitching)

Checkpoint: Thermal Via Arrays Under Power Pads

Thermal Via Design Guidelines

Thermal Resistance Calculation

Single via thermal resistance (through 1.6mm board):
  R_via = L / (k * A)

  Where:
    L = Board thickness = 1.6mm
    k = Copper conductivity = 385 W/(m*K)
    A = Copper barrel cross-section area

  For 0.3mm drill, 25um plating:
    A = pi * 0.025 * (0.3 - 0.025) = 0.0216 mm2
    R_via = 1.6 / (385 * 0.0216) = 0.19 C/W per via

  For filled via (0.3mm, conductive fill):
    A = pi * (0.15)^2 = 0.071 mm2 (full area)
    R_via = 1.6 / (385 * 0.071) = 0.058 C/W per via (3x better!)

  Array of 9 vias (3x3 grid):
    R_array = 0.19/9 = 0.021 C/W (unfilled)
    R_array = 0.058/9 = 0.006 C/W (filled)
            

QFN Thermal Pad Layout Example

QFN-32 (5x5mm body, 3.2x3.2mm exposed pad):

+-----------------------------------+
|  [Pin]  [Pin]  [Pin]  [Pin]  [Pin]  |
|                                     |
| [Pin]  +---------------------+ [Pin] |
|        | o   o   o   o   o  |       |
| [Pin]  | o   o   o   o   o  | [Pin] |
|        | o   o   o   o   o  |       |
| [Pin]  | o   o   o   o   o  | [Pin] |
|        | o   o   o   o   o  |       |
| [Pin]  +---------------------+ [Pin] |
|                                     |
|  [Pin]  [Pin]  [Pin]  [Pin]  [Pin]  |
+-----------------------------------+

25 thermal vias (5x5 grid) at 0.6mm pitch
Via drill: 0.3mm, Pad: 0.5mm
Fill: Conductive epoxy or solder-plugged
Bottom: Matching copper pad for heat spreading
            

Checkpoint: Back-Drill Specification

When Back-Drill is Required

A via stub acts as an unterminated transmission line that creates a resonance at:

f_resonance = c / (4 * L_stub * sqrt(Dk))

Where:
  c = speed of light (3e8 m/s)
  L_stub = stub length
  Dk = dielectric constant (~4.0 for FR-4)

Example: 1.0mm stub in FR-4
  f_res = 3e8 / (4 * 0.001 * sqrt(4.0)) = 37.5 GHz (quarter-wave)

Rule of thumb: Back-drill when stub > lambda/10 at highest frequency
  For 10 Gbps signals (~5 GHz fundamental): stub < 3mm is acceptable
  For 25 Gbps signals (~12.5 GHz): stub < 1.2mm (back-drill usually needed)
  For 56 Gbps PAM4 (~14 GHz): stub < 1mm (back-drill essential)
            

Back-Drill Specifications

Via Strategy Review Summary & Tool Configuration

Via Definition in EDA Tools

HDI Via Types and Selection Guide

Via Strategy Quick Reference