Tutorial 5.9: DRC & Design Rule Verification
Comprehensive guide to running, interpreting, and resolving Design Rule Check violations for manufacturing readiness
Comprehensive guide to running, interpreting, and resolving Design Rule Check violations for manufacturing readiness
Design Rule Check (DRC) is the automated verification that your PCB layout meets all defined constraints for manufacturing, electrical performance, and assembly. A clean DRC (zero violations) is a mandatory prerequisite before generating fabrication outputs. Every violation represents either a real manufacturing defect or a rule that needs refinement.
The DRC engine is only as good as its configuration. A DRC that reports zero violations against incorrect or incomplete rules provides false confidence. The review of DRC results must include verification that the rules themselves are correctly defined for the design's requirements and the selected fabricator's capabilities.
| Violation Type | Manufacturing Impact | Typical Yield Loss |
|---|---|---|
| Clearance violation (<4mil) | Copper bridging (short circuit) | 2-5% of boards affected |
| Annular ring violation (<3mil) | Broken pad connection (open) | 1-3% of affected vias |
| Acid trap | Over-etched trace (open or thin) | 0.5-2% at affected locations |
| Copper sliver | Loose copper causing random shorts | Variable, hard to detect |
| Unconnected net | Non-functional board (100% failure) | 100% if not caught in test |
The goal is ZERO DRC violations before tape-out. Every violation must be either:
Never simply ignore or suppress violations without documented justification.
The final DRC report shows zero errors and zero unresolved warnings. Any waived violations have documented engineering justification. DRC was run with ALL rule categories enabled (not selectively disabled).
Tools > Design Rule Check. Enable all categories in the DRC dialog. The "Report" pane shows all violations grouped by rule. Double-click a violation to zoom to its location. Use "Violation Overlay" mode to see all violations highlighted on the PCB. Export report as HTML or CSV for review documentation.
Inspect > Design Rules Checker. Click "Run DRC" to check all rules. KiCad groups violations by type (Errors, Warnings, Exclusions). Right-click a violation to "Exclude" with comment (creates documented waiver). Use "Show All" to see violations on the board. Export report as text file.
Tools > Update DRC for real-time checking (checks as you work). Tools > Design Rule Check for batch DRC. Violations appear in the Constraint Manager spreadsheet with hyperlinks to board locations. Use Display > Status > DRC Errors for summary counts. Export report via Tools > Quick Reports > DRC.
Under schedule pressure, designers sometimes disable rules that generate many violations (e.g., "Minimum Annular Ring" or "Silk over Pads") to achieve a "clean" DRC report. This creates a false sense of readiness. The fabricator's DFM check will catch these issues and either reject the design or produce boards with defects. Always fix the violations or properly waive them - never hide them by disabling the rule.
No copper-to-copper clearance violations exist anywhere in the design. This includes trace-to-trace, trace-to-pad, pad-to-pad, copper-pour-to-trace, and via-to-trace clearances on all layers.
| Violation Type | Common Cause | Fix Strategy |
|---|---|---|
| Trace-to-trace too close | Dense routing in BGA breakout | Use approved neck-down rules for the breakout region |
| Copper pour to trace | Pour clearance less than routing clearance | Set pour clearance >= routing clearance + 1mil tolerance |
| Pad-to-pad overlap | Components placed too close | Move components or use smaller footprint variant |
| Via-to-trace on inner layer | Via anti-pad too small for trace clearance | Increase anti-pad or reroute trace away from via |
| Copper-to-board-edge | Pour extends too close to board edge | Increase board edge pullback on copper pour settings |
| Plane-to-plane clearance | Different voltage planes too close on same layer | Increase gap between plane shapes (min 8-10mil) |
DRC report shows 0 clearance violations across all 8 layers. BGA breakout region has a defined "Advanced" rule set with 3.5mil/3.5mil clearance (documented fabricator approval). All copper pours are freshly regenerated. Plane layers show clean clearance between voltage domains.
DRC report shows 47 clearance violations. 23 are in the DDR region (designer says "it will be fine"). 15 are copper pour issues on inner layers (not visible, so ignored). 9 are trace-to-board-edge (assumed "fabricator will handle it"). None are documented or waived.
All nets in the netlist are fully connected (zero unrouted connections). No ratsnest lines remain. Any intentionally unconnected pins are explicitly marked with "no-connect" flags in the schematic. The design matches the schematic netlist exactly.
| Cause | How to Identify | Resolution |
|---|---|---|
| Missing route | Visible ratsnest line between two pins | Route the connection |
| Broken trace (DRC violation) | Trace appears connected but DRC shows break | Repair trace, check for accidental deletion |
| Wrong footprint pin mapping | Ratsnest connects to unexpected pin | Fix footprint pin numbering in library |
| Copper pour not connecting | Pad appears in pour but not connected | Check thermal relief settings or direct connect rule |
| Via not connected to net | Via present but DRC shows it as floating | Assign via to correct net or reconnect trace |
| Schematic change not synced | Net exists in PCB but not schematic (or vice versa) | Re-sync netlist from schematic (ECO) |
A component's ground pin appears connected because it sits on a copper pour. However, if the pour has thermal relief that is too restrictive (minimum connection = 2 spokes), and the pad is in an area where the pour cannot reach (isolated by anti-pads), the pin may actually be unconnected. Always run DRC AFTER regenerating all copper pours to catch these "phantom connections."
All manufacturing-specific design rules pass: minimum annular ring, acid traps, copper slivers, starved thermals, and minimum feature sizes are all within fabricator capability.
| Rule | Minimum (Standard) | Recommended | Description |
|---|---|---|---|
| Annular ring (outer) | 4 mil (0.1mm) | 5 mil (0.125mm) | Copper ring around drill hole |
| Annular ring (inner) | 3.5 mil (0.09mm) | 4 mil (0.1mm) | Less critical (no soldering) |
| Acid trap angle | > 90 degrees | > 100 degrees | No acute angles at trace junctions |
| Copper sliver width | 3 mil (0.075mm) | 4 mil (0.1mm) | Thin copper fragments that may detach |
| Copper sliver length | Cannot exceed 50x width | 20x width | Long thin slivers are worse |
| Minimum copper feature | 3.5 mil (0.09mm) | 4 mil (0.1mm) | Smallest copper that can be reliably etched |
| Starved thermal spoke | 8 mil width minimum | 10 mil width | Thermal relief spoke too thin |
| Solder mask sliver | 3 mil (0.075mm) | 4 mil (0.1mm) | Mask web between pads |
Annular ring = (Pad diameter - Drill diameter) / 2
Minimum annular ring must account for drill registration tolerance:
Effective ring = Annular ring - Drill position tolerance
Example:
Pad diameter: 0.6mm
Drill diameter: 0.3mm
Annular ring: (0.6 - 0.3) / 2 = 0.15mm (6 mil) -- GOOD
Pad diameter: 0.45mm
Drill diameter: 0.3mm
Annular ring: (0.45 - 0.3) / 2 = 0.075mm (3 mil) -- MARGINAL
With drill tolerance of +/- 0.05mm:
Worst case: 0.075 - 0.05 = 0.025mm (1 mil) -- WILL FAIL!
IPC-6012 Class 2 requirement: minimum 50um (2mil) annular ring
IPC-6012 Class 3 requirement: minimum 50um (2mil) annular ring (with tighter drill tolerance)
Acid traps occur at trace junctions where the angle between traces is less than 90 degrees (acute angle). During PCB etching, the etchant pools in these acute corners and over-etches, potentially breaking the trace. Modern fabricators with spray etching are less susceptible, but acid traps remain a DFM violation per IPC standards.
Copper slivers are thin, elongated copper features that can:
Prevention: Set copper pour minimum connection width and eliminate thin copper features in pour settings. Most tools have a "minimum spoke/connection width" parameter for pours.
Altium: Enable manufacturing rules in Design Rules > Manufacturing: Minimum Annular Ring, Acute Angle, Minimum Solder Mask Sliver, Board Edge Clearance. Import your fabricator's DFM rules file if available.
KiCad: DRC includes manufacturing checks by default (annular ring, minimum drill, track width). Custom rules can be added in Board Setup > Custom Rules using the rule language.
Allegro: Manufacture > Run DFM Checks provides dedicated manufacturing verification beyond standard DRC. Includes acid trap, sliver, and annular ring analysis.
All copper features (traces, pours, pads, vias) maintain minimum clearance from the board outline. This prevents copper exposure at routed edges and ensures structural integrity at the board perimeter.
| Feature | Min Clearance | Fabricator Typical | Reason |
|---|---|---|---|
| Copper trace | 0.2mm (8mil) | 0.25mm (10mil) | Router tolerance + copper pullback |
| Copper pour | 0.25mm (10mil) | 0.5mm (20mil) | Standard pour pullback |
| Via (drill edge) | 0.3mm (12mil) | 0.5mm (20mil) | Drill registration + structural |
| PTH pad (pad edge) | 0.5mm (20mil) | 1.0mm | Prevents copper exposure + cracking |
| Component body | 0.5mm | 1.0mm | Pick-and-place clearance |
Non-plated holes and mounting holes maintain adequate clearance from all copper features on all layers. Plated holes maintain correct anti-pad clearance on non-connected layers. No risk of drill hitting copper that would create unintended connections.
| Scenario | Minimum Clearance (drill edge to copper) | Notes |
|---|---|---|
| NPTH to trace (all layers) | 0.25mm (10mil) | Must clear on every layer the drill passes through |
| NPTH to copper pour | 0.3mm (12mil) | Pour must have relief around NPTH |
| PTH anti-pad to trace | 0.15mm (6mil) | Between anti-pad edge and nearest trace |
| PTH to PTH (different nets) | 0.2mm (8mil) drill-to-drill | After accounting for drill tolerance |
| Mounting hole to copper | 0.5mm (20mil) | Extra clearance for isolation + screw torque stress |
A non-plated mounting hole is added to the board. The designer adds keep-outs on the top and bottom layers, but forgets that the drill passes through ALL inner layers. On an inner power plane, the drill passes directly through the copper with no clearance. Result: the mounting screw contacts the power plane copper, creating a short to the chassis or unpredictable behavior. Solution: NPTH holes must have clearance (anti-pad) on EVERY layer they pass through, including inner planes.
DRC Resolution Priority Order:
================================
1. CONNECTIVITY ERRORS (Critical - board will not function)
- Unconnected nets (missing routes)
- Short circuits (unintended connections)
- Net assignment errors
Priority: Fix ALL before proceeding to other categories
2. CLEARANCE VIOLATIONS (Critical - board may not be manufacturable)
- Copper-to-copper clearance
- Copper-to-edge clearance
- Drill-to-copper clearance
Priority: Fix ALL - these cause fabrication rejections
3. MANUFACTURING VIOLATIONS (Major - affects yield and reliability)
- Minimum annular ring
- Acid traps
- Copper slivers
- Minimum feature size
Priority: Fix ALL - these cause defects in production
4. PLACEMENT/MECHANICAL (Major - affects assembly and fit)
- Component courtyard overlap
- Component-to-edge clearance
- Height violations
Priority: Fix ALL - these cause assembly failures
5. HIGH-SPEED/SI VIOLATIONS (Major - affects performance)
- Impedance width violations
- Length matching out of tolerance
- Diff pair symmetry
Priority: Fix or waive with simulation evidence
6. COSMETIC/ADVISORY (Minor - affects aesthetics/documentation)
- Silkscreen overlap
- Silkscreen over pads
- Text size violations
Priority: Fix for professionalism, waive only if non-impactful
DRC Waiver Record
=================
Violation ID: DRC-2024-001
Rule Violated: Minimum Clearance (Trace-to-Trace) - 5mil required, 4mil actual
Location: Layer 3, coordinates (45.2mm, 22.8mm)
Nets Involved: DDR4_DQ7, DDR4_DQ6
Justification: BGA escape zone. Fabricator (JLCPCB Advanced) confirmed
3.5mil capability in writing (Ref: Quote #QT-20240315-001).
Signal integrity simulation shows acceptable crosstalk at 4mil
spacing for 0.8mm segment length.
Risk Assessment: Low. Within fabricator confirmed capability.
Approved By: [Engineer Name, Date]
| Category | Manufacturing DRC | Electrical DRC |
|---|---|---|
| Purpose | Ensure board can be fabricated correctly | Ensure board functions correctly |
| Annular ring | Verifies drill-to-pad relationship | Not applicable |
| Clearance | Prevents etching/plating defects | Prevents short circuits and arcing |
| Connectivity | Not applicable | Verifies all nets are complete |
| Impedance | Not applicable | Verifies controlled-Z trace widths |
| Slivers | Prevents copper fragment defects | Not applicable |
| Length matching | Not applicable | Verifies timing constraints |
| Acid traps | Prevents over-etching | Not applicable |
Before submitting to a fabricator, use their online DFM checker for a second opinion:
| Service | URL/Access | What It Checks | Cost |
|---|---|---|---|
| JLCPCB Order System | Upload Gerber at order page | Outline, drill, clearance, annular ring, min feature | Free |
| PCBWay Instant Quote | Upload at quote page | Layer count, board size, special features | Free |
| EuroCircuits PCB Visualizer | eurocircuits.com | Full DFM analysis with detailed report | Free |
| Sierra Circuits DFM Check | protoexpress.com | Advanced DFM with clearance/annular ring | Free |
| Altium 365 DRC | altium.com/365 | Full DRC in browser without Altium license | Free (limited) |
CRITICAL: DRC results depend on copper pour state!
Before pour regeneration:
- Stale pours may show false "unconnected" errors (pad not in pour)
- Old pour shape may not have clearance to newly routed traces
- Islands may exist that have since been connected by routing
After pour regeneration:
- All clearances recalculated against current routing
- Connections to pads verified against current net assignments
- Islands identified accurately
- Slivers from tight pour clearance correctly detected
ALWAYS regenerate ALL copper pours/zones BEFORE running final DRC.
Sequence: Regenerate pours -> Run DRC -> Fix violations -> Repeat
| Violation | Quick Fix | Root Cause Fix |
|---|---|---|
| Clearance (trace-trace) | Move trace to increase gap | Review if routing density requires more layers |
| Clearance (pour-trace) | Increase pour clearance setting | Ensure pour clearance >= trace clearance + tolerance |
| Unconnected net | Route the missing connection | Verify schematic connectivity is correct |
| Minimum annular ring | Increase pad size | Reduce drill size or use larger via padstack |
| Acid trap | Change junction angle to >=90 deg | Use 45-degree routing mode exclusively |
| Copper sliver | Delete or widen the thin feature | Increase minimum pour connection width |
| Silk over pad | Move text away from pad | Set DRC rule to auto-clip with clearance margin |
| Board edge clearance | Move copper inward | Set proper edge pullback in pour settings |
| Drill-to-copper | Move via or trace | Increase NPTH keep-out zone on all layers |
| Length mismatch | Add serpentine tuning | Re-route for more direct path to reduce total length |
For production release, the DRC report must be archived as part of the design documentation: