Checkpoint 1: Thermal Vias (0.3mm Drill, 1mm Pitch) Critical
Thermal vias are the primary mechanism for conducting heat through the PCB from the component side to inner copper planes and the opposite side. Their design directly determines the effectiveness of the PCB as a heat sink.
Via Thermal Resistance Formula
Single Plated-Through Via:
Rth_via = L / (k_cu × A_cu × n)
Cross-sectional area of copper in one via:
A_cu = π × d_drill × t_plating
Where:
L = Length of via (board thickness) [m]
k_cu = 385 W/(m·K) for copper
d_drill = Drill diameter [m]
t_plating = Copper plating thickness [m] (typically 20-25µm)
n = Number of vias
Standard thermal via (0.3mm drill, 25µm plating, 1.6mm board):
A_cu = π × 0.0003 × 0.000025 = 2.356 × 10⁻⁸ m²
Rth_single = 0.0016 / (385 × 2.356×10⁻⁸) = 176 °C/W per via
For n = 16 vias in parallel:
Rth_array = 176 / 16 = 11.0 °C/W
For n = 25 vias:
Rth_array = 176 / 25 = 7.0 °C/W
Copper-filled vias (solid copper):
A_cu = π × (0.3mm)² / 4 = 7.07 × 10⁻⁸ m²
Rth_single_filled = 0.0016 / (385 × 7.07×10⁻⁸) = 58.8 °C/W
For 16 filled vias: 58.8/16 = 3.7 °C/W
Filled vias are 3× better than plated-only!
Optimal Thermal Via Design
- Determine the thermal pad size of the component (from datasheet recommended footprint).
- Calculate via grid: Use 0.8-1.0mm pitch. For a 5×5mm pad, this gives a 5×5 or 4×4 array (16-25 vias).
- Set via drill to 0.3mm (12mil) with 0.6mm (24mil) pad. This balances thermal performance with manufacturability.
- Specify via fill: For QFN/BGA (via-in-pad), use copper-filled and plated over (IPC-4761 Type VII). For non-via-in-pad, solder-filled or capped vias are acceptable.
- Connect to all available ground/power planes (L2, L3, L4 in a 4-layer board) with full connection (no thermal relief on power/ground vias).
- Add via stitching around the thermal pad area (every 2-3mm) to connect ground pours on all layers.
Via Array Configurations
| Thermal Pad Size | Recommended Array | Via Count | Rth_via (plated) | Rth_via (filled) |
|---|
| 3×3mm (QFN-16) | 3×3, 1mm pitch | 9 | 19.6 °C/W | 6.5 °C/W |
| 4×4mm (QFN-32) | 4×4, 1mm pitch | 16 | 11.0 °C/W | 3.7 °C/W |
| 5×5mm (QFN-48) | 5×5, 1mm pitch | 25 | 7.0 °C/W | 2.4 °C/W |
| 7×7mm (QFN-64) | 7×7, 1mm pitch | 49 | 3.6 °C/W | 1.2 °C/W |
| 10×10mm (BGA EPAD) | 10×10, 1mm pitch | 100 | 1.8 °C/W | 0.6 °C/W |
QFN-48 motor driver with 5.15×5.15mm thermal pad: 25 thermal vias in 5×5 grid at 1.0mm pitch, 0.3mm drill, copper-filled and plated over per IPC-4761 Type VII. Vias connect to ground planes on L2 (0.2mm prepreg) and L3 (0.8mm from surface). No thermal relief on inner layer connections. Bottom layer has matching copper pour with solder mask opening for additional radiation.
QFN thermal pad with only 4 vias at corners (non-filled, open holes). During reflow, solder wicks through the open vias creating solder balls on the bottom side and voids under the thermal pad. Thermal resistance is 44°C/W instead of the expected 7°C/W. Component runs 30°C hotter than designed.
- Open vias under thermal pads: Solder wicking through open vias causes voids and solder balls. Always specify filled or capped vias for via-in-pad applications.
- Thermal relief on thermal vias: Thermal relief spokes on inner layer connections reduce thermal conductivity by 50-70%. Use solid connections for thermal vias.
- Undersized via pads: If annular ring is too small, the via may drill out during fabrication, losing the inner-layer connection entirely.
- Via-to-via spacing too tight: Excessive via density can weaken the PCB structurally. Maintain 0.2mm minimum copper-to-copper spacing between via pads.
Checkpoint 2: Copper Pour for Heat Spreading Major
Copper pours act as in-plane heat spreaders, distributing localized heat from components over a larger board area for more effective convection and radiation to the ambient.
Copper Thermal Conductivity by Weight
Copper Properties:
Thermal conductivity: k = 385 W/(m·K)
Thickness per weight:
0.5 oz = 17.5µm = 0.7mil
1.0 oz = 35µm = 1.4mil
2.0 oz = 70µm = 2.8mil
3.0 oz = 105µm = 4.2mil
In-plane thermal conductance (per unit width):
k×t for 1oz = 385 × 0.000035 = 0.01348 W·m/(m·K) = 13.5 W·mm/(mm·K)
k×t for 2oz = 27.0 W·mm/(mm·K)
Comparison: FR4 (entire 1.6mm thickness):
k_FR4 = 0.3 W/(m·K) through-plane, 0.7 W/(m·K) in-plane
k×t for FR4 = 0.7 × 1.6 = 1.12 W·mm/(mm·K)
One layer of 1oz copper conducts 12× more heat in-plane than all the FR4!
Spreading Resistance Calculations
Lateral spreading resistance in a copper layer:
For a circular source (radius r_s) spreading to radius r_sp:
R_spread = ln(r_sp / r_s) / (2π × k × t)
Example: 3mm radius source (QFN thermal pad) spreading to 25mm radius on 1oz copper:
R_spread = ln(25/3) / (2π × 385 × 0.000035)
R_spread = 2.12 / 0.0847 = 25.0 °C/W (single layer)
With 4 layers connected by vias:
R_spread_effective ≈ 25.0 / 3.5 = 7.1 °C/W
(Not exactly /4 because not all layers have equal connectivity)
Minimum Pour Requirements
| Component Power | Min Pour Radius (1oz/2L) | Min Pour Radius (1oz/4L) | Achieved Rth_board-to-air |
|---|
| 0.25W | 8mm | 5mm | 80-120 °C/W |
| 0.5W | 12mm | 8mm | 60-90 °C/W |
| 1.0W | 18mm | 12mm | 40-60 °C/W |
| 2.0W | 25mm | 18mm | 25-40 °C/W |
| 5.0W | 40mm | 28mm | 15-25 °C/W |
| 10W | Heatsink needed | 40mm | 10-18 °C/W |
- Assign copper pour zones around hot components on all layers. Priority: ground planes should be solid; split planes lose thermal effectiveness.
- Maximize copper coverage: Target >80% copper fill on inner layers. Remove unnecessary splits and use wider trace clearances only where needed for impedance.
- Connect pours across layers with via stitching at 3-5mm intervals throughout the thermal zone.
- Route signal traces around thermal zones -- do not cut through copper pour areas connected to hot components.
- Consider 2oz copper on inner layers for high-power designs (adds ~$3-5/board for standard fab).
- Open solder mask on bottom copper pours (opposite hot components) for improved radiation cooling.
Buck converter area: High-side and low-side MOSFETs connected to a 35×25mm copper pour on L1 (switch node). Ground plane on L2 is unbroken in a 50×40mm zone under the entire converter. L3 and L4 also have dedicated ground pour zones connected through 40+ via stitches. Thermal imaging shows even temperature distribution across the zone, max hotspot only 15°C above ground plane average.
Power regulator copper pad is 10×8mm (barely larger than component). Three signal traces routed directly through the pour create 0.2mm-wide thermal bottlenecks. Ground plane on L2 has a split directly under the regulator for analog/digital separation. Heat cannot spread; component runs at 140°C while the board 10mm away is only 50°C.
Checkpoint 3: Inner Layer Thermal Connections Major
The connection between thermal vias and inner copper planes must be solid (no thermal relief) for power/ground thermal paths. The inner plane design determines the overall thermal spreading capability of the PCB.
Connection Types and Their Impact
Direct Connection (no thermal relief):
Full annular ring connected to plane → maximum heat flow
Rth_connection ≈ 0 (negligible compared to via barrel)
Thermal Relief (4 spokes, 0.25mm wide):
Heat must flow through 4 narrow spokes: 0.25mm wide × 35µm thick × ~0.2mm long
Rth_spoke = L / (k × A) = 0.0002 / (385 × 0.25×10⁻³ × 35×10⁻⁶)
Rth_spoke = 0.0002 / (3.37×10⁻⁶) = 59.3 °C/W per spoke
Rth_4_spokes = 59.3 / 4 = 14.8 °C/W per via connection
Impact on 16-via array:
Without relief: Rth_plane_connect ≈ 0°C/W
With relief: Rth_plane_connect = 14.8/16 = 0.93°C/W per layer
For 2 inner layers: 0.93/2 = 0.46°C/W additional
Thermal relief adds ~5-10% to total via array Rth -- significant for high-power ICs.
When to Use/Omit Thermal Relief
| Application | Thermal Relief? | Reason |
|---|
| Thermal pad vias to ground plane | NO - Direct connect | Maximum thermal conductivity needed |
| Power component drain/source to plane | NO - Direct connect | Current carrying + thermal path |
| Signal via to ground (hand solder) | YES - 4 spoke | Enables hand soldering/rework |
| Through-hole component on ground plane | YES - 4 spoke | Prevents heat wicking during wave solder |
| Via stitching (ground vias, not populated) | NO or minimal | Not soldered, thermal benefit of direct |
| Component pad on inner plane (SMD) | Depends | Not applicable -- SMD doesn't contact inner layers |
Design rules configured: "Thermal vias" net class has "No thermal relief" rule on all inner layers. Standard signal vias retain 4-spoke relief (0.25mm spoke, 0.3mm gap) for rework compatibility. The distinction is clearly documented in the PCB design notes and the fabrication drawing calls out: "Thermal via pads: direct connection to planes (no relief)."
Default CAD settings used for all vias: 4-spoke thermal relief everywhere. The 25 thermal vias under a QFN are all connected with thin spokes to the ground plane. Total effective thermal resistance increases by 25% compared to direct connection. The component runs 8°C hotter than predicted, pushing it over the junction temperature limit.
Checkpoint 4: Thermal Relief on Non-Power Pads Minor
While thermal vias need direct connections, through-hole component pads on large copper planes need thermal relief to enable proper soldering. Without relief, the plane acts as a massive heat sink, preventing solder from wetting properly.
Thermal Relief Design Parameters
Standard Thermal Relief (IPC-7351 recommended):
Spoke width: 0.25mm minimum (0.3mm preferred)
Gap/anti-pad: 0.25-0.5mm (clearance to plane)
Number of spokes: 4 (90° spacing) or 2 (180° spacing)
Spoke angle: 45° rotation from pad X-axis (standard)
Thermal impact calculation:
4-spoke relief, 0.3mm wide spokes, 1oz copper:
R_thermal_per_spoke = L_gap / (k × w × t)
L_gap = 0.3mm (antipad - pad radius)
R_spoke = 0.0003 / (385 × 0.3×10⁻³ × 35×10⁻⁶) = 74 °C/W
R_4_spokes = 74/4 = 18.5 °C/W per pad-to-plane connection
Without relief (direct connect):
R ≈ 0.5°C/W (spreading into infinite plane from annular ring)
Where Thermal Relief Is Critical
- Through-hole connectors: Large ground pins on connectors (USB, RJ45, power) connected to ground planes need relief for wave/hand soldering.
- Through-hole capacitors: Electrolytic caps on power planes need relief for proper solder flow.
- Test points: Through-hole test points on planes need relief for hand-solder attachment.
- Mounting holes (plated): If connected to ground, need relief for assembly tooling contact.
Through-hole USB connector ground pins: 4-spoke thermal relief (0.3mm spoke, 0.4mm gap) on both ground plane layers. Wave solder process window verified: 2.5 seconds contact time achieves full hole fill. Spoke width sufficient for 0.5A ground current per pin without significant voltage drop.
Through-hole connector with direct connection to 2oz ground plane (no relief). During wave soldering, insufficient heat reaches the pad top -- solder does not wet through the hole. Results in cold joints and intermittent ground connections. Board fails vibration testing.
- Insufficient spoke width for current: Power pins carrying significant current through thermal relief spokes. If each spoke carries 1A: V_drop = I × R = 1 × (L/k×A) is negligible for copper, but verify for high-current (>5A) applications.
- Missing relief on one layer only: If inner Layer 2 has relief but Layer 3 does not, soldering may still be difficult as Layer 3 wicks heat. Apply consistently to all connected layers.
- 2-spoke vs 4-spoke: 2-spoke relief provides better thermal isolation but worse current capacity and mechanical pad attachment. Use 4-spoke for general purpose.
Checkpoint 5: Hot Spot Identification Major
Identifying potential thermal hot spots early in the design phase allows layout optimization before prototype fabrication. Hot spots occur where high-power components are clustered or where thermal spreading is inadequate.
Hot Spot Risk Factors
- Component clustering: Multiple power components (regulators, MOSFETs, power ICs) placed close together without adequate spacing. Their thermal zones overlap, creating cumulative heating.
- Board edges and corners: Components near board edges have reduced spreading area (heat can only spread inward). Corner placement reduces effective area by 75%.
- Under other components: A hot component on the bottom directly below a temperature-sensitive component on top creates coupling.
- Restricted airflow: Components behind tall capacitors, connectors, or enclosure walls that block convective cooling.
- Copper voids: Areas where routing channels, keep-outs, or plane splits prevent heat spreading.
- Enclosed spaces: Components under shields, in pockets, or sandwiched between boards (mezzanine stacks).
Hot Spot Mitigation Strategies
Minimum spacing between hot components:
Rule of thumb: Space hot components at least 2× the spreading radius apart.
Spreading radius ≈ √(P × Rth_spread / ΔT_allowable × π × k × t)
Example: Two 2W components on 4-layer PCB
Target: Each component's thermal zone does not raise adjacent component >5°C
At 15mm from a 2W source on 4-layer: ΔT ≈ 2W × ln(15/3)/(2π×385×140µm) ≈ 10°C
At 25mm: ΔT ≈ 2W × ln(25/3)/(2π×385×140µm) ≈ 6.3°C
Space 2W components at least 25mm apart if mutual heating is a concern.
| Strategy | Benefit | Implementation |
|---|
| Spread hot components apart | Reduces thermal interaction | Place regulators, drivers at board edges |
| Place hot parts on board edge | Better convection access | Power supply at board perimeter |
| Separate hot/sensitive zones | Protects precision circuits | ADCs, references away from power |
| Add thermal isolation slots | Blocks in-plane heat flow | Routed slots between zones (2-3mm wide) |
| Use heavier copper locally | Better spreading | 2oz copper on power layers |
| Dedicate one layer to thermal | Unbroken heat path | Solid ground plane, no splits in hot zone |
Power supply section (buck converter, LDOs, total 8W) placed along one edge of the board with clear thermal boundary. Ground plane under power section is solid with no signal routing through it. A 3mm routed slot separates the power zone from the sensitive analog section. Thermal imaging shows max 95°C in power zone and only 45°C in analog zone.
Three voltage regulators (1W each) placed in a triangle, 8mm apart, in the center of the board. Two are under an EMI shield that blocks convection. The shield area reaches 115°C. A precision voltage reference is placed 5mm away -- its accuracy degrades due to thermal gradient, causing ADC errors.
Checkpoint 6: Board-Level Thermal Resistance Estimated Major
The overall board-level thermal resistance (from board surface to ambient) combines convection and radiation from all exposed surfaces. This is the final link in the thermal chain and is often the dominant resistance.
Board-to-Air Thermal Resistance
Combined convection + radiation:
Rth_board_to_air = 1 / ((h_conv + h_rad) × A_effective)
Natural convection coefficient for PCB:
h_conv = 5-12 W/(m²·K) depending on orientation and ΔT
Typical: 8 W/(m²·K) for vertical board, moderate ΔT
Radiation coefficient:
h_rad = ε × σ × (T_s² + T_surr²) × (T_s + T_surr)
For ε = 0.9 (solder mask), T_s=80°C, T_surr=25°C:
h_rad = 0.9 × 5.67×10⁻⁸ × (353² + 298²) × (353 + 298)
h_rad = 0.9 × 5.67×10⁻⁸ × 213,413 × 651 = 7.1 W/(m²·K)
Total: h_total = 8 + 7.1 = 15.1 W/(m²·K)
(Radiation is nearly as important as convection!)
Example: 50×50mm effective thermal area:
A = 0.05 × 0.05 × 2 (both sides) = 0.005 m²
Rth_board_to_air = 1 / (15.1 × 0.005) = 13.2 °C/W
Quick Estimation for Standard PCBs:
2-layer, 1oz, 50×50mm board:
Rth_board ≈ 40-60 °C/W (per side, natural convection)
4-layer, 1oz, 50×50mm board:
Rth_board ≈ 25-40 °C/W (better spreading, both sides)
4-layer, 2oz, 100×100mm board:
Rth_board ≈ 8-15 °C/W (large area, good spreading)
Scaling rule: Rth roughly inversely proportional to board area
Double the area → halve the Rth (approximately)
Factors That Improve Board Rth
- Board area: Larger boards have lower Rth. If possible, extend ground pours to board edges.
- Copper weight: 2oz vs 1oz gives ~40% improvement in spreading, reducing effective Rth.
- Number of layers: 4-layer vs 2-layer gives 50-70% improvement due to additional copper planes.
- Surface emissivity: Dark solder mask (green, blue, black) emits radiation well (ε≈0.85-0.9). Bare copper is poor (ε≈0.05).
- Orientation: Vertical boards convect 20-30% better than horizontal (hot-side-up). Horizontal hot-side-down is worst.
- Air gap: Boards parallel to walls within 5mm have reduced convection. Maintain >10mm clearance.
Industrial sensor PCB (100×60mm, 4-layer, 1oz) dissipating 3W total: Thermal analysis estimates Rth_board = 18°C/W based on 70% copper fill on inner layers and 50% on outer layers. With 85°C ambient: T_board = 85 + 3×18 = 139°C max hot spot. Verified by measurement: actual = 133°C (simulation conservative by 6°C, which is expected).
Small IoT module (25×25mm, 2-layer) dissipating 1.5W: Rth_board = 80°C/W due to small area and limited copper. T_board = 65 + 1.5×80 = 185°C -- board substrate (FR4, Tg=170°C) is at risk. PCB delamination observed after thermal cycling.
