Checkpoint 1: Test Points on All Critical Nets Critical
Every critical net (power rails, clock lines, data buses, control signals, analog references) must have a dedicated test point accessible for production testing and field debugging. Test points enable ICT, flying probe, and functional test access.
Test Point Requirements
| Net Category | Test Point Required? | Minimum Size | Preferred Location |
|---|
| Power rails (all) | Yes - mandatory | 1.0mm pad | Near regulator output AND load |
| Ground (multiple) | Yes - multiple points | 1.0mm pad | Distributed, near measurement points |
| Clock signals | Yes - mandatory | 0.9mm pad | Near source, consider loading |
| Reset lines | Yes - mandatory | 1.0mm pad | Accessible for manual override |
| I2C/SPI buses | Yes - each signal | 0.9mm pad | Near connector/header side |
| UART TX/RX | Yes - mandatory | 1.0mm pad | Accessible for debug console |
| Analog inputs/outputs | Yes - mandatory | 1.0mm pad | After filtering, before ADC |
| High-speed differential | Conditional | 0.5mm via (no pad) | Only if needed, use series resistor pad |
| General GPIO | Conditional | 0.9mm pad | If used for functional test stimulus |
Test Point Design Specifications
ICT (In-Circuit Test) Test Point Requirements:
Pad diameter: minimum 0.9mm (35mil), preferred 1.0mm (40mil)
Pad shape: round (preferred) or square
Surface finish: HASL, ENIG, or OSP (solderable)
Solder mask: Opening should be 0.1mm larger than pad per side
Spacing: minimum 2.54mm (100mil) center-to-center
Preferred: 1.27mm (50mil) grid aligned for fixture pins
Via-as-test-point:
Acceptable if: via pad ≥ 0.9mm, not tented (solder mask open)
Not acceptable if: via is filled/capped, pad < 0.9mm, or covered by component
Test point height clearance:
Probe side (typically bottom): 3mm minimum component clearance around TP
This allows the probe to land without hitting adjacent components.
- Create a test point list from the schematic: identify all nets requiring production test access.
- Assign test points to the probe side of the board (typically bottom side for ICT bed-of-nails).
- Place test points on 2.54mm or 1.27mm grid where possible to simplify fixture design.
- Ensure 3mm clearance around each test point (no tall components blocking probe access).
- Verify no test points are under components, heatsinks, or in areas covered by conformal coating.
- Label test points in silkscreen (TP1, TP2, etc.) and maintain a test point map document.
All power rails (1.2V, 1.8V, 3.3V, 5V, 12V) have dedicated test pads on the bottom layer. Each rail has 2 test points: one near the regulator output and one at the far end of the distribution (to detect voltage drop). UART debug port has 4 test pads (TX, RX, GND, VCC) grouped on 2.54mm pitch for easy clip attachment. 85% of nets have test access.
No dedicated test points added. Testing relies on probing component pads (0201 caps, BGA balls). ICT fixture cannot contact 40% of nets. Flying probe test takes 8 minutes per board (vs. 30 seconds with ICT). Production bottleneck and 15% untestable defects escape to functional test.
- Test point on high-speed signal: Adding a test pad (and its stub) can degrade signal integrity. For signals >1GHz, use a series resistor pad as the test point, or accept that these nets will be tested via JTAG boundary scan only.
- Shared test points: Two nets should never share a test point. Each test point must connect to exactly one net for unambiguous testing.
- Test points under shields: EMI shields installed after ICT block probe access. Place test points outside shielded zones, or test before shield installation.
- Bottom-side components blocking probes: If both sides have components, there may be insufficient probe-side access. Plan test point placement early in layout.
Checkpoint 2: ICT Grid Spacing (100mil Preferred) Major
In-Circuit Test fixtures use spring-loaded probes (pogo pins) arranged in a grid. Test points should align to this grid for reliable contact and fixture simplicity.
ICT Fixture Design Constraints
Standard ICT probe specifications:
100mil (2.54mm) grid: Standard probe, 0.69mm tip, most reliable
75mil (1.91mm) grid: High-density, 0.50mm tip
50mil (1.27mm) grid: Ultra-high-density, 0.39mm tip
Probe specifications by grid:
100mil: Travel = 2.3mm, Force = 6oz (170g), Life = 1M+ cycles
75mil: Travel = 1.5mm, Force = 4oz (113g), Life = 500K cycles
50mil: Travel = 1.0mm, Force = 3oz (85g), Life = 200K cycles
Minimum test point spacing rules:
Between two test points: ≥ grid pitch (100mil preferred)
Test point to board edge: ≥ 3mm (fixture clamping zone)
Test point to tooling hole: ≥ 5mm
Test point to tall component: ≥ 3mm (probe access angle)
Grid Alignment Best Practices
- Define a test point grid origin (typically a tooling hole or board corner).
- Set PCB editor grid to 2.54mm (100mil) when placing test points.
- Place all test points on-grid wherever possible. Off-grid points require custom probe locations and increase fixture cost.
- Group test points by functional area to simplify fixture wiring.
- Maintain at least 100mil between any two test points. Never place test points at 50mil spacing unless using 50mil-grid fixture.
- Verify board tooling holes match fixture plate tooling. Standard: 3.2mm holes on corners, 2-3 per board.
Fixture Cost vs. Test Point Density:
Standard 100mil grid: ~$3,000-5,000 fixture cost
Mixed 100/75mil grid: ~$5,000-8,000 fixture cost
50mil grid fixture: ~$8,000-15,000 fixture cost
Custom (off-grid) fixture: ~$10,000-20,000 fixture cost
Number of probes impacts fixture cost and maintenance:
< 100 probes: Simple fixture, low maintenance
100-500 probes: Standard production fixture
500-1000 probes: High-density, requires precision alignment
> 1000 probes: Multi-stage or flying probe may be more economical
Board has 120 test points, all placed on 2.54mm grid (±0.1mm tolerance). Test points concentrated on board bottom side with minimum 2.54mm spacing between adjacent points. Three tooling holes (3.2mm, unplated) on board corners for fixture registration. Fixture quote: $4,200 with 2-week lead time.
185 test points scattered randomly, 30% off-grid, 15 pairs at less than 75mil spacing. Fixture vendor quotes $14,500 and warns that probe-to-probe clearance issues may require multi-hit testing (probe half the points, then shift and probe the other half). Test time doubles.
Checkpoint 3: Boundary Scan (JTAG) Chain Complete Major
JTAG boundary scan (IEEE 1149.1) enables testing of interconnections between ICs without physical probe access. All JTAG-capable devices should be connected in a proper chain with correct topology.
JTAG Chain Design
Standard JTAG signals:
TCK - Test Clock (input to all devices, single source)
TMS - Test Mode Select (input to all devices, daisy-chain or star)
TDI - Test Data In (serial chain: debugger → first device → ... → last device)
TDO - Test Data Out (serial chain: last device → debugger)
TRST# - Test Reset (optional, active-low, connect to all devices)
Chain topology:
TDI → Device_1 → Device_2 → ... → Device_N → TDO
(TCK and TMS connected to all devices in parallel/star)
Chain order considerations:
1. FPGA first (if FPGA needs programming via JTAG)
2. Processor second (for debug access priority)
3. Other devices in order of testability importance
4. Shortest TDI/TDO path between adjacent devices in chain
JTAG Design Rules
- Identify all JTAG-capable devices on the board (FPGAs, CPUs, DSPs, PHYs, some memories).
- Connect TDI→TDO chain in logical order. Keep traces short between adjacent devices.
- Add pull-up resistors (4.7-10kΩ) on TMS and TDI to VCC to prevent floating during reset.
- Add pull-up on TRST# (10kΩ) if used, to keep devices out of test mode during normal operation.
- Buffer TCK if chain is long (>5 devices) or traces are long (>150mm). TCK is a clock and must have clean edges.
- Provide a 10-pin or 20-pin JTAG header (ARM standard or MIPI-20) with all signals accessible.
- Add capability to bypass devices in chain (using jumpers or multiplexers) for individual device debug.
JTAG Header Pinouts
| Pin | ARM 10-pin (Cortex) | ARM 20-pin (Legacy) | Notes |
|---|
| 1 | VCC (target ref) | VCC | Voltage reference for debugger |
| 2 | SWDIO/TMS | VCC | |
| 3 | GND | nTRST | |
| 4 | SWCLK/TCK | GND | |
| 5 | GND | TDI | |
| 6 | SWO/TDO | GND | |
| 7 | Key (no pin) | TMS | |
| 8 | NC/TDI | GND | |
| 9 | GND | TCK | |
| 10 | nRESET | GND | |
JTAG chain: TDI → FPGA (XC7A35T) → ARM Cortex-M4 (STM32F407) → Ethernet PHY (KSZ9031) → TDO. 4.7kΩ pull-ups on TDI, TMS. 10kΩ pull-up on TRST#. ARM 10-pin Cortex header (1.27mm pitch) for debug. Separate FPGA programming header (Xilinx 14-pin) for parallel programming. Chain bypass multiplexer (SN74LVC1G3157) allows isolating FPGA from processor chain.
FPGA JTAG connected correctly, but processor JTAG pins left floating (not connected to chain or header). Cannot debug processor in-system. Engineer must desolder and reprogram in a socket programmer. Board-level interconnect between FPGA and processor cannot be tested via boundary scan because the chain is incomplete.
- TCK signal integrity: TCK must have clean edges and adequate drive strength for the entire chain. Long traces or heavy loading can cause setup/hold violations. Add buffer if TCK trace >100mm or >5 devices.
- TRST# glitches: If TRST# glitches during power-up, devices may enter test mode unexpectedly. Use RC filter (10kΩ + 100nF) to debounce.
- Missing BSDL files: Boundary scan testing requires BSDL (Boundary Scan Description Language) files for each device. Verify these are available from IC vendors before committing to boundary scan test strategy.
- TCK frequency compatibility: All devices in chain must support the TCK frequency. Older devices may be limited to 10MHz while modern FPGAs support 33MHz+.
Checkpoint 4: Bed-of-Nails Accessibility Major
For ICT (In-Circuit Test) using a bed-of-nails fixture, test points must be physically accessible from one side of the board without obstruction from components, connectors, or mechanical features.
Accessibility Requirements
Component Height Restrictions (Probe Side):
Within 2mm of test point center: No components taller than 1mm
Within 3mm of test point center: No components taller than 2mm
Within 5mm of test point center: No components taller than 5mm
Board Edge Keep-Out:
No test points within 3mm of board edge (fixture clamping zone)
No test points within 5mm of tooling holes
No test points within 10mm of board connectors (fixture clearance)
Fixture Plate Requirements:
Fixture plate thickness: typically 12-15mm
Probe compression: 2-3mm typical
Total clearance needed above TP: 15-18mm (fixture plate + probe + preload)
Vacuum seal gasket area: 3mm from board edge (no TPs here)
Test Access Analysis
- Define the probe side (typically bottom) and identify all test points on that side.
- Create a component height map for the probe side showing keep-out zones around each tall component.
- Identify test points that conflict with component keep-out zones and relocate them or change probe type.
- Verify no test points are under connectors, heat sinks, mounting hardware, or labels/barcodes.
- Check that the board supports vacuum hold-down (no large openings or cut-outs that prevent seal).
- For double-sided probing (needed when bottom side is dense): verify top-side probe access with component heights.
Test Access Score Calculation:
Access Score = (Number of accessible TPs / Total required TPs) × 100%
Target: ≥ 95% for ICT
Minimum acceptable: 85% (remaining nets tested by boundary scan or functional test)
Below 70%: ICT fixture not economical, consider flying probe
Alternative test strategies by access level:
95-100%: Full ICT fixture (fastest, most economical at volume)
80-95%: ICT + boundary scan supplement
60-80%: Flying probe (no fixture, slower but flexible)
< 60%: Functional test only (higher defect escape rate)
Bottom side designed specifically for ICT access: All test points on 100mil grid, minimum 2.54mm spacing. Tallest component on bottom = 1.5mm (tantalum cap). No components within 3mm of any test point. Board edge clear 5mm from nearest TP. Vacuum seal area unobstructed. Test access score: 97% (remaining 3% tested via JTAG).
Dense double-sided assembly with BGA on top and fine-pitch QFP on bottom. Test points placed as afterthought -- 25% are under or adjacent to bottom-side ICs. Three test points are under the SD card socket. Board cannot be vacuum-sealed due to a large milled slot. Test access: 62%. Flying probe adds $2.50/board and 5 minutes/board to production.
Checkpoint 5: Functional Test Points Accessible Minor
Beyond ICT, functional test (FCT) requires access to specific signals for stimulus injection and response measurement. These test points may need special characteristics (impedance-matched, filtered, buffered) beyond simple probe pads.
Functional Test Access Types
| Signal Type | Access Method | Requirements | Example |
|---|
| Analog output | Probe pad + buffer | Low impedance drive, no loading | DAC output verification |
| Analog input | Series resistor (0Ω default) | Allow test signal injection | ADC input stimulus |
| Digital bus | Test connector or header | Full bus access for pattern gen | Memory bus functional test |
| RF signal | SMA/U.FL connector | Matched impedance, calibrated | Antenna port, mixer output |
| Power sequencing | Scope probe points | Ground reference nearby | Boot sequence verification |
| Communication | Debug port header | Standard pinout (USB, UART) | Firmware download, log access |
Design Techniques for Functional Test
Series Resistor Injection Point:
Place 0Ω resistor in series on test-critical analog signals.
During test: Replace with appropriate resistor to inject stimulus.
Normal operation: 0Ω passes signal unmodified.
Loop-Back Test Points:
Connect output to input (TX→RX) via 0Ω resistor for self-test:
- UART TX to RX (with level-appropriate connection)
- Ethernet TX± to RX± via transformer or relay
- CAN TX to RX (bus transceiver loop-back mode)
Ground Reference:
Every analog test point needs a GND reference within 5mm.
Place GND test points adjacent to signal test points for
oscilloscope ground clip or differential probe attachment.
Functional test design: UART debug header (4-pin, 2.54mm) near board edge for firmware access. 0Ω resistors in series on both ADC inputs for signal injection during calibration. SMA connector on RF output (50Ω matched) for power/frequency measurement. LED test mode activates all LEDs simultaneously for optical inspection. Self-test loop-back connections on Ethernet and CAN with test-mode enable via GPIO.
No functional test provisions. Board must be fully assembled and loaded with firmware before any functional verification is possible. When boards fail, there is no way to isolate the problem -- is it firmware, hardware, or assembly? Debug requires cutting traces and soldering bodge wires. Field failure analysis is impractical.
Checkpoint 6: Test Coverage >95% Estimated Major
Test coverage quantifies what percentage of potential defects can be detected by the combined test strategy. The target is >95% coverage through a combination of ICT, boundary scan, and functional test.
Coverage Calculation
Test Coverage by Method:
ICT Coverage:
- Opens/shorts: 98-100% (for accessible nets)
- Component presence: 95-100%
- Component value: 90-95% (R, C values measured)
- IC functionality: 0% (ICT only checks connections)
Boundary Scan Coverage:
- Interconnect between JTAG devices: 95-98%
- Stuck-at faults: 85-95%
- Non-JTAG device connections: 0%
Functional Test Coverage:
- Circuit functionality: 80-95%
- Parameter verification: 60-90%
- Firmware execution: 100%
Combined Coverage Formula:
C_total = 1 - (1-C_ICT) × (1-C_JTAG) × (1-C_FCT)
Example: C_ICT=85%, C_JTAG=20%, C_FCT=75%
C_total = 1 - (0.15 × 0.80 × 0.25) = 1 - 0.03 = 97% ✓
Defect Coverage by Test Type
| Defect Type | ICT Detect? | JTAG Detect? | FCT Detect? | Coverage Gap? |
|---|
| Solder short | Yes (98%) | Yes (adjacent JTAG pins) | Maybe (depends on effect) | Low risk |
| Solder open | Yes (95%) | Yes (JTAG devices) | Yes (if functional impact) | Low risk |
| Wrong component | Yes (R/C values) | No | Maybe (if behavior changes) | Medium risk for ICs |
| Missing component | Yes (95%) | Yes (JTAG missing) | Yes (function fails) | Low risk |
| Tombstoned passive | Yes (open circuit) | N/A | Yes (function impact) | Low risk |
| Wrong polarity | Maybe (diode check) | No | Yes (damage/malfunction) | Medium risk |
| Solder void (BGA) | No (resistance OK) | No (connection OK) | No (works initially) | HIGH RISK - X-ray needed |
| Cold joint | Maybe (high R) | No | Maybe (intermittent) | HIGH RISK |
| ESD damage | No | No | Maybe (parametric shift) | HIGH RISK |
DPMO (Defects Per Million Opportunities) Escapes:
Typical assembly defect rate: 50-200 DPMO (good CM)
With 95% test coverage: Escapes = DPMO × (1 - Coverage) = 100 × 0.05 = 5 DPMO
With 99% test coverage: Escapes = 100 × 0.01 = 1 DPMO
For a board with 2000 solder joints:
At 100 DPMO: Expected defects per board = 2000 × 100/1,000,000 = 0.2
Boards with defects ≈ 18% (Poisson distribution)
After 95% test: Escaped defects = 0.2 × 0.05 = 0.01 per board
Field failure rate ≈ 1% (1 in 100 boards has an undetected defect)
Test strategy document specifies: ICT covers 85% of nets (all power, ground, and signal nets with test points). JTAG boundary scan covers FPGA-to-memory interconnect (200+ pins) not accessible via ICT. Functional test verifies: communication ports, analog calibration, power sequencing, LED/display operation. Combined estimated coverage: 97.5%. Residual risk addressed by burn-in test (2 hours at 55°C) to catch latent defects.
Only functional test performed (no ICT or JTAG). Coverage estimated at 75%. One in four defective boards escapes to the customer. Field failure rate is 5× higher than industry average. Warranty costs exceed test equipment investment that would have been needed for proper ICT.
