Track 12: Noise Sources & PCB EMI Problems

Cause

Internal transistor switching creates rapid current transients (di/dt) on power supply pins. High-speed digital ICs can draw ampere-level current spikes in sub-nanosecond periods during logic transitions.

Effect

Voltage droop and ringing on VCC rail, conducted emissions on power bus, radiated emissions from power plane resonance. Can cause logic errors in adjacent ICs sharing the same supply.

Mitigation

• Place decoupling caps within 3mm of power pins
• Use multiple cap values to cover wide frequency range
• Minimize loop area between cap, VCC pin, and GND pin
• Use power/ground plane pairs with thin dielectric

Cause

Clock signals produce odd harmonics extending to very high frequencies. Data buses with simultaneous switching (SSN) create broadband noise. The harmonic envelope follows a sinc function determined by rise/fall time.

Effect

Narrowband emissions at clock harmonics that can fail FCC/CISPR limits. Broadband noise floor elevation. Coupling to adjacent sensitive analog circuits.

Mitigation

• Use spread-spectrum clocking (SSC) to reduce peak harmonics
• Slow edge rates to minimum acceptable values
• Route clocks on inner layers between ground planes
• Terminate clock lines properly to prevent reflections
• Series resistors on bus outputs to reduce dI/dt

Cause

Common-mode (CM) currents flow on cable shields when there is a voltage difference between ground references. Even microamps of CM current on a cable can radiate significantly because cables act as efficient antennas.

Effect

Cables become the dominant source of radiated emissions in most products. A cable of length L becomes an efficient antenna when L > lambda/10. CM currents of just 5 uA can fail FCC Class B at 3m.

Mitigation

• Use common-mode chokes (ferrite beads) at cable entry
• Ensure 360-degree shield termination at connectors
• Filter all signals crossing the enclosure boundary
• Minimize ground impedance at connector interface
• Use shielded cables with low transfer impedance

Cause

Every current-carrying trace forms either a loop antenna (with its return path) or a dipole antenna. The radiation efficiency depends on the electrical length relative to wavelength and the loop area.

Effect

PCB traces radiate electromagnetic fields proportional to frequency squared (loop) or frequency (dipole). Emissions increase 20-40 dB per decade of frequency for loop-type radiation.

Mitigation

• Minimize loop area: route signals over continuous ground plane
• Keep trace lengths below lambda/20 for critical signals
• Use stripline (buried between planes) for high-speed signals
• Avoid routing traces near board edges
• Match trace impedance to prevent standing waves

Cause

Slots, splits, or gaps in the ground plane force return current to detour around the discontinuity, creating a large loop area. The split itself also acts as a slot antenna.

Effect

Dramatically increased loop area leads to higher radiated emissions (20-30 dB increase typical). The slot can radiate as a resonant slot antenna. Crosstalk between circuits on opposite sides of the split increases severely.

Mitigation

• Never route high-speed signals across ground plane splits
• Use a continuous, unbroken ground plane
• If split is necessary, bridge with capacitors or stitching vias
• Place split perpendicular to signal flow, never parallel
• Use separate planes for analog/digital, connected at a single point

Cause

When a signal transitions between layers via a through-hole via, the return current must also change reference planes. Without a nearby path between the planes, the return current must find a distant path, creating a large loop.

Effect

Increased radiation from the enlarged return current loop. Signal integrity degradation due to impedance discontinuity. Crosstalk to other signals near the via transition area.

Mitigation

• Place GND stitching vias within 50 mils of every signal via
• Add decoupling caps between reference planes near signal vias
• Prefer layer transitions between layers that share the same reference (e.g., L1-L2 both reference GND)
• Minimize layer transitions for high-speed signals
• Use back-drilled vias to reduce stub length