Module 7: DFM, DFT & Reliability

All trace widths ≥ fabricator minimum (documented); all spaces ≥ fabricator minimum; annular ring ≥ IPC Class 2 requirement

Via drill diameter ≥ fabricator minimum; aspect ratio (board thickness / drill diameter) ≤ 8:1 for standard process; no micro-vias unless HDI process confirmed

Copper fill ≥ 40% on each layer; copper balance between top/bottom within 20%; thieving or fill patterns added to sparse areas to prevent warpage

Solder mask expansion ≥ 50um per side from pad edge; solder mask dams between fine-pitch pads ≥ 75um width; no solder mask slivers

Silkscreen line width ≥ 150um; character height ≥ 0.8mm; no silkscreen over exposed pads; all reference designators readable without rotation ambiguity

Panel design includes tooling holes, fiducials, and breakaway tabs/V-score; tab width and perforation match fabricator spec; no components within 5mm of tab/score line

No acute-angle trace junctions (< 90 degrees) that trap etchant; all trace bends ≥ 90 degrees or use curved routing; DRC check passes for acid traps

All copper ≥ 250um from board edge (milled) or ≥ 400um from V-score line; no components within 3mm of routed edge; mounting holes have keep-out respected

Layer stackup (material, thickness, prepreg/core sequence) confirmed achievable by selected fabricator; impedance targets achievable within ±10% with specified stackup

Non-connected drill holes maintain ≥ 200um clearance to nearest copper on all layers; anti-pads sized correctly in plane layers

Fab drawing includes: stackup table, drill chart, material callouts, surface finish, impedance requirements, IPC class, acceptance criteria, and special instructions

Test points present on 100% of power rails, reset, and debug UART; accessible to bed-of-nails fixture (100-mil grid); pad diameter ≥ 35mil

In-circuit test access to ≥ 95% of nets; test pads on single side (preferably bottom); minimum 50mil pitch between test points

JTAG/SWD debug header populated or footprint available; all JTAG chain devices connected with correct TDI/TDO ordering; TRST pull-down present if required

All JTAG-capable ICs included in boundary scan chain; BSDL files available for all devices; chain verified with test software (≥ 95% fault coverage)

LED indicators present for: each power rail (or power-good), processor heartbeat/activity, communication link status, and fault conditions

Debug UART accessible via header or test pads; baud rate documented; boot log output enabled by default; console accessible without disassembly

Communication interfaces (UART, SPI, Ethernet, CAN) support loopback test mode via hardware or firmware; external loopback connectors or jumper provisions available

Test points on all analog signal paths (ADC inputs, DAC outputs, sensor signals); test point impedance does not load circuit (> 10x source impedance)

Flash/EEPROM programming header or pads accessible in production fixture; programming time documented and ≤ 30 seconds per unit for volume production

Board revision identifiable via hardware (resistor coding, GPIO strapping, or EEPROM); firmware can read board revision at runtime for compatibility

Zero-ohm resistors or jumpers allow isolation of each major subsystem (power, RF, analog) for independent testing; isolation points documented in test procedure

Functional test plan covers 100% of product features; pass/fail criteria quantified with tolerances; test time budget ≤ 2 minutes per unit for production

Minimum 3 global fiducials (asymmetric placement) on panel; local fiducials on fine-pitch components (≤ 0.5mm pitch); fiducial diameter 1.0mm with 2mm clearance

All polarized components (diodes, ICs, electrolytics) oriented in consistent direction per IPC-7351; pin 1 indicators clearly marked on silkscreen and paste layer

Minimum 1.0mm clearance between adjacent component bodies; 2.0mm clearance around BGA/QFN for rework access; tall components do not shadow neighbors during reflow

Stencil apertures match pad geometry with appropriate area ratio (≥ 0.66); step-down or step-up regions defined for mixed-pitch; aperture corners rounded for release

Exposed pad (QFN/BGA) thermal vias: diameter 0.3mm, pitch 1.0-1.2mm grid; vias tented or plugged on opposite side to prevent solder wicking; paste coverage 50-80% of pad area

All SMT components on one side where possible; if double-sided, bottom-side components < 5g weight and < 10mm height to survive second reflow without adhesive

Through-hole components grouped for wave/selective solder access; no SMT pads in wave solder path without protection; lead protrusion 1.0-2.0mm above board

Symmetric pad geometry for 0402/0603 passives (pad length, width, and thermal relief match); trace connections routed symmetrically to both pads; no via-in-pad on small passives

All components on same side compatible with single reflow profile; no mix of high-temp and low-temp solder requirements; MSL (Moisture Sensitivity Level) managed per J-STD-020

Assembly drawing includes: component placement coordinates (centroid file), BOM with approved alternates, special handling instructions, and inspection criteria per IPC-A-610 class

Calculated MTBF > product warranty period x 3; electrolytic cap life at Tmax > product design life; calculation method documented (MIL-HDBK-217 or Telcordia)

All components derated per NASA or NAVSEA guidelines: capacitors ≤ 50% Vrated, resistors ≤ 50% Prated, semiconductors ≤ 75% Tjmax; derating spreadsheet complete

Electrolytic cap calculated life (L = L0 x 2^((Trated-Tactual)/10)) exceeds product design life by ≥ 50%; ripple current within rating; ESR degradation accounted for

BGA/QFN solder joint fatigue life calculated for expected thermal cycling range (Coffin-Manson); life exceeds 10-year target; underfill specified for high-stress applications

Conformal coating type and thickness specified if operating in harsh environment (humidity > 85%, condensation, salt spray); keep-out areas for connectors and test points defined

Heavy components (> 3g) have mechanical anchoring (adhesive, clips, or additional solder pads); PCB natural frequency > 3x excitation frequency; no resonance at expected vibration profile

Design survives expected thermal cycling range (e.g., -40 to +85C) for > 1000 cycles without solder joint or via failure; CTE mismatch analysis performed for critical components

Connector mating cycle rating > expected lifetime insertions x 2; contact resistance increase over life within acceptable range; appropriate connector type for use case

Highly Accelerated Life Test parameters defined (temperature step stress, vibration levels, combined stress); acceptance criteria quantified; HASS production screen profile derived from HALT results

All components with MSL > 1 identified; floor life tracked; baking procedures defined if exposure exceeds limits; dry-pack shipping requirements specified on BOM

All known wear-out mechanisms identified (electromigration, NBTI, HCI for ICs; whisker growth for tin finish); mitigation strategies documented; end-of-life detection implemented where feasible

Every component verified as 'Active' lifecycle status on manufacturer website or distributor; no NRND or EOL parts; lifecycle status date-stamped in BOM

Critical components available from ≥ 2 independent manufacturers or ≥ 3 authorized distributors; sole-source parts identified with risk mitigation plan (last-time-buy quantity calculated)

All components with lead time > 12 weeks identified; buffer stock strategy defined; alternative components pre-qualified for long-lead items; supply chain disruption plan documented

All components sourced through authorized distribution channels; incoming inspection defined for high-risk parts (visual, XRF, decap); AS6171 testing for broker-sourced components

Component consolidation performed (unique part count minimized); passive values standardized to E24 series; package sizes standardized where possible; total BOM cost within target

Product lifecycle forecast aligned with component availability forecasts; PCN (Product Change Notification) monitoring active; form-fit-function alternates documented for all ICs

All components checked against export control lists (EAR/ITAR/EU Dual-Use); ECCN/USML classification documented; no restricted components without proper license; country-of-origin verified

No single-country dependency for > 70% of BOM value; alternate sources from different geographic regions identified for critical components; tariff impact assessed

Pre-compliance radiated and conducted emissions measured and ≥ 6dB below applicable limits (FCC Part 15/CISPR 32 Class B); immunity tested to IEC 61000-4 series at target levels

Applicable safety standards identified (UL/IEC 62368-1, 60601-1, 61010-1); creepage/clearance distances meet standard for pollution degree and voltage; safety-critical components are certified

All materials and components verified RoHS 3 compliant (EU 2015/863); no SVHC above 0.1% w/w per REACH; material declarations (IPC-1752) collected from all suppliers

RF modules pre-certified (FCC/IC/CE/MIC) or certification test plan budgeted; antenna placement meets module manufacturer requirements; RF shielding adequate for spurious emissions

Product meets target ESD level on all user-accessible ports (minimum ±4kV contact, ±8kV air per IEC 61000-4-2); protection verified on all connector pins; no functional upset at target level

PCB laminate meets UL 94 V-0 rating; enclosure material meets required flammability class; all plastics within 6mm of heat sources rated for operating temperature + 25C margin

Enclosure IP rating meets product requirement (e.g., IP67 for outdoor); gasket compression and material specified; connector sealing rated to same IP level; verified by test or analysis

All required regulatory marks identified (CE, FCC, UL, WEEE, recycling); label placement, size, and durability meet standard requirements; serial number and traceability scheme defined