The target impedance is the maximum allowable impedance the Power Distribution Network (PDN) can present to the IC across all frequencies of interest. If the PDN impedance exceeds this target at any frequency, voltage ripple will exceed the allowable specification, potentially causing logic errors, timing failures, or device malfunction.
The Target Impedance Formula
Z_target = V_ripple / I_transient
Where:
V_ripple = Allowable voltage ripple (typically 3-5% of VDD)
I_transient = Maximum transient current demand (worst-case step load)
Step-by-Step Calculation
Determine the nominal supply voltage (VDD). For example, a 1.0V core supply for an FPGA.
Determine the allowable ripple percentage from the IC datasheet. Typical values: 3% for DDR memory, 5% for general logic, 2% for sensitive analog supplies. For 1.0V at 5%: V_ripple = 1.0V x 0.05 = 50mV.
Determine the maximum transient current. This is the worst-case current step the IC demands. For an FPGA with 20A steady-state and 50% load step: I_transient = 20A x 0.5 = 10A.
This impedance must be maintained from DC up to the maximum frequency of interest (typically the clock frequency or the inverse of the rise time: f_knee = 0.35/t_rise).
FPGA Core Rail (1.0V, 20A, 5% ripple):
Z_target = (1.0V x 0.05) / (20A x 0.5) = 5 milliohms
f_knee = 0.35 / 0.3ns = 1.17 GHz
PDN impedance must stay below 5 milliohms from DC to ~1 GHz.
Design uses: 6x 470uF bulk + 20x 10uF mid + 80x 100nF HF + 20x 1nF UHF caps plus 4-layer plane pair.
Using only ripple spec without considering transient:
Designer calculates: Z_target = 50mV / 2A (average current, not transient) = 25 milliohms
Actual transient demand is 10A, so real Z_target should be 5 milliohms.
Result: 5x higher impedance target leads to insufficient decoupling, voltage droop during switching.
Real-World Design Parameters
Supply Rail
VDD
Ripple %
I_transient
Z_target
FPGA Core (VCCINT)
0.85V
3%
15A
1.7 mOhm
DDR4 VDD
1.2V
3%
4A
9 mOhm
3.3V I/O
3.3V
5%
2A
82.5 mOhm
1.8V Aux
1.8V
5%
3A
30 mOhm
Using average current instead of transient current: I_transient is the CHANGE in current demand (di/dt), not the steady-state draw.
Ignoring frequency range: Target impedance must be met across the entire bandwidth, not just at a single frequency.
Not accounting for worst-case conditions: Use maximum temperature operating conditions where ESR increases and capacitance decreases.
Confusing ripple budget allocation: If VRM contributes 2% ripple, only 1% remains for PDN decoupling ripple on a 3% total budget.
Interactive Target Impedance Calculator
Calculator: Enter your supply rail parameters to compute the PDN target impedance and knee frequency.
Target Impedance
Knee Frequency
Sigrity PowerSI: Use "PDN Impedance Analysis" with port placed at IC power pin. Set target impedance as horizontal limit line. Sweep from 100Hz to 10GHz.
Ansys SIwave: Create PI analysis, define voltage source at VRM, current sink at IC. Use "Compute PDN Impedance" to get Z vs frequency.
HyperLynx PI: Use "PDN Analysis Wizard" - enter VDD, ripple%, max current to auto-calculate Z_target.
Checkpoint 2: Impedance Profile Flat Across Frequency Critical
A well-designed PDN exhibits a flat impedance profile below the target impedance from DC to the highest frequency of concern. Each frequency band is served by a different PDN component: VRM at low frequencies, bulk capacitors in the kHz range, MLCC decoupling in MHz, and plane capacitance at GHz.
Frequency Bands and Responsible PDN Elements
Frequency Band
PDN Element
Typical Values
DC - 10 kHz
VRM (Voltage Regulator Module)
Output impedance < 5 mOhm
10 kHz - 1 MHz
Bulk Capacitors (100uF - 1000uF)
Electrolytic/Polymer caps
1 MHz - 100 MHz
Mid-frequency MLCC (1uF - 10uF)
0402-0805 ceramic X5R/X7R
100 MHz - 1 GHz
High-frequency MLCC (10nF - 100nF)
0201-0402 ceramic C0G/X7R
> 1 GHz
Plane Capacitance + On-die caps
Thin dielectric plane pair
How to Verify Flat Impedance
Plot the impedance of each individual capacitor group (bulk, mid, HF) including ESR and ESL mounting parasitics.
Compute the parallel combination of all capacitor groups plus plane capacitance.
Overlay the VRM output impedance (increases with frequency above its bandwidth).
The composite impedance curve should remain below Z_target at all frequencies.
Identify any peaks that exceed the target - these indicate gaps in frequency coverage.
Gap between bulk and MLCC coverage:
- 2x 100uF electrolytic (f_SRF ~ 50kHz) with no mid-frequency capacitors
- Jump directly to 100nF MLCC (effective from 5MHz+)
- Gap from 200kHz to 5MHz has impedance rising to 50 mOhm (10x above target)
Result: Significant voltage droop during medium-frequency transients (bus switching, clock toggles).
Plotting only ideal capacitance: Real capacitor impedance includes ESR and ESL. A 100nF cap acts as an inductor above 22 MHz.
Ignoring mounting inductance: A 0402 cap with 0.2nH body inductance can have 0.8nH total mounting inductance with poor via/pad design.
Not accounting for DC bias derating: A 10uF X5R 0402 cap at 1.0V bias may only provide 7uF effective capacitance. At 3.3V it may drop to 3uF.
Checkpoint 3: No Anti-Resonance Peaks Major
Anti-resonance (or parallel resonance) occurs when two capacitors of different values are connected in parallel. At the anti-resonance frequency, the inductive impedance of the larger capacitor (above its SRF) resonates with the capacitive impedance of the smaller capacitor (below its SRF), creating an impedance peak that can exceed the target impedance.
Anti-Resonance Frequency Calculation
For two capacitors C1 (large) and C2 (small) in parallel:
f_anti = 1 / (2*pi*sqrt(ESL1 * C2))
Peak impedance at anti-resonance:
Z_peak = sqrt(ESL1/C2) * Q_factor
Where Q = 1/ESR * sqrt(L/C) at the resonant frequency
In simulation, plot the impedance of individual cap groups and combined PDN.
Look for peaks between the SRF of the larger value cap group and the SRF of the smaller value cap group.
The peak occurs where the inductive slope of one group crosses the capacitive slope of the adjacent group.
Measure the peak magnitude - if it exceeds Z_target, remediation is needed.
Add intermediate capacitor values to bridge the frequency gap and dampen the peak.
Mitigation Strategies
Add intermediate values: Between 10uF and 100nF, add 1uF capacitors. Their SRF fills the gap.
Use capacitors with higher ESR: Controlled-ESR caps (like Murata NFM series) damp the resonance.
Increase quantity of smaller caps: More parallel caps reduce the effective inductance, lowering the anti-resonance peak.
Use RC snubber networks: A series RC across the problematic frequency can dampen specific peaks.
Smooth transition with intermediate values:
Capacitor values: 470uF -> 47uF -> 10uF -> 2.2uF -> 470nF -> 100nF -> 10nF -> 1nF
Each step is approximately 5x-10x ratio, ensuring SRF overlap.
Maximum anti-resonance peak: 3.2 mOhm (within 5 mOhm target).
Large value gap creates dangerous peak:
Capacitor values: 100uF -> 100nF (1000x jump)
Anti-resonance peak at ~5 MHz: 120 mOhm (24x above 5 mOhm target)
This causes ringing on the power rail at 5 MHz whenever the IC switches.
Sigrity OptimizePI: Enable "Anti-resonance Detection" in impedance sweep. Tool highlights peaks exceeding target with red markers.
Ansys SIwave: In PI analysis results, use "Peak Detection" feature. Right-click peaks to identify contributing components.
HyperLynx PI: Use "What-if Analysis" to add/remove capacitor groups and observe anti-resonance changes in real-time.
Checkpoint 4: VRM Bandwidth Adequate Major
The Voltage Regulator Module (VRM) controls PDN impedance at low frequencies (DC to its bandwidth). Above the VRM's control loop bandwidth, the output impedance rises - and bulk capacitors must take over. The handoff between VRM and bulk caps must be seamless with no impedance gap.
Obtain the VRM control loop bandwidth from the datasheet or Bode plot measurement (typically specified as 0dB crossover frequency).
Calculate VRM output impedance at the bandwidth frequency: Z_VRM(f_BW) = V_out / (A_OL * I_load) where A_OL is open-loop gain.
Determine where VRM impedance will equal Z_target: f_crossover = f_BW * (Z_target / R_out).
Verify that bulk capacitor impedance is below Z_target at this crossover frequency.
Ensure at least 1 decade of overlap between VRM effective range and bulk cap effective range.
Proper VRM-to-bulk-cap handoff:
VRM: TPS53819A multi-phase buck, f_BW = 300kHz, R_out = 1 mOhm
VRM impedance reaches 5 mOhm target at: f = 300kHz * (5/1) = 1.5 MHz
Bulk caps: 6x 470uF polymer, effective from 10kHz, Z < 3 mOhm up to 5 MHz
Overlap: 10kHz to 1.5 MHz (2+ decades) -- smooth handoff with no gap.
VRM bandwidth gap:
VRM: LM1117 LDO, f_BW = 50kHz (with required 10uF tantalum output), R_out = 15 mOhm
VRM exceeds target at: 50kHz * (5/15) = 16.7kHz -- already above target at 17kHz!
Bulk caps only effective from 100kHz upward.
Gap: 17kHz to 100kHz has impedance reaching 40 mOhm -- severe ripple in this band.
Assuming LDO bandwidth equals GBW: LDO bandwidth depends heavily on output capacitor ESR. Some LDOs require specific ESR ranges for stability.
Not considering VRM location: Long traces/planes between VRM and IC add inductance, reducing effective VRM bandwidth at the load.
Ignoring VRM output capacitor contribution: The VRM output capacitor bank is part of both the VRM response and the PDN impedance.
Checkpoint 5: Spreading Inductance Minimized Major
Spreading inductance is the parasitic inductance of the power/ground plane pair between the decoupling capacitor and the IC power pin. Even a perfectly designed capacitor is useless if the interconnect inductance to the load is too high. This inductance limits the effectiveness of decoupling capacitors at high frequencies.
Spreading Inductance Formula
For a plane pair (microstrip approximation):
L_spread = (mu_0 * h) / (2 * pi) * ln(r / r_via)
Where:
mu_0 = 4*pi*10^-7 H/m (permeability of free space)
h = dielectric thickness between power and ground planes
r = distance from capacitor via to IC power via
r_via = via barrel radius
Simplified rule of thumb for FR4:
L_spread (pH) = 8.5 * h(mils) * ln(d/r_via)
Place decoupling capacitors as close to IC power pins as physically possible (target < 100 mils / 2.5mm).
Use thin dielectric between power/ground plane pair (< 4 mils preferred, 2 mils ideal).
Use via-in-pad for capacitor mounting to eliminate trace inductance from pad to via.
Use multiple vias per capacitor pad (2 vias per pad for 0402, 3-4 for 0805).
Place capacitors on the same side of the board as the IC when possible to avoid through-board via inductance.
For BGA packages, place capacitors in the BGA escape field directly under the IC.
Optimized capacitor placement for BGA FPGA:
- 0201 capacitors placed within BGA field (distance to power vias: 0.5-1.5mm)
- Via-in-pad on all decoupling caps (adds 0 trace inductance)
- Power/GND plane pair on layers 2-3 with 3mil dielectric (63pH/square)
- Resulting spreading inductance per cap: 30-80 pH
- Effective capacitor bandwidth extends to 800+ MHz
Capacitors placed far from IC with traces:
- 0805 capacitors placed 15mm from FPGA (accessible for hand rework)
- Connected via 10-mil trace, 5mm long, to nearest via
- Trace inductance alone: ~5nH (trace) + 0.5nH (via) = 5.5nH
- At 100MHz: Z = 2*pi*100e6*5.5e-9 = 3.5 ohms -- completely ineffective!
- These caps only contribute below 1MHz despite being 100nF (designed for 10-100MHz).
Sigrity PowerSI: Use "Current Path Visualization" to see actual current flow from cap to IC. "Inductance Extraction" gives exact via + plane inductance.
Ansys SIwave: "PDN Inductance Map" shows spreading inductance contours. Place caps in low-inductance zones (blue regions).
General Rule: Capacitor effectiveness radius = c / (10 * f * sqrt(er)) where c = speed of light, f = frequency, er = dielectric constant.
Checkpoint 6: PDN Simulation Performed Critical
PDN simulation validates the design against the target impedance across the full frequency range. Without simulation, it is impossible to verify that the combination of VRM, decoupling capacitors, planes, vias, and traces meets the impedance target. Every design with Z_target below 20 mOhm should be simulated.
Simulation Workflow
Import Layout: Import PCB layout (ODB++, Gerber, or native format) into PI simulation tool.
Define Power Nets: Assign power and ground nets. Verify plane shapes are correctly identified.
Place Ports: Add impedance observation ports at IC power pin locations (VRM output, IC power balls).
Assign Component Models: Apply S-parameter or SPICE models for all decoupling capacitors with correct ESR/ESL values.
Define VRM Model: Set VRM as voltage source with output impedance (R + L model or S-parameter).
Configure Frequency Sweep: Set sweep from 100Hz to 10GHz with sufficient resolution (100 points per decade minimum).
Run Simulation: Execute impedance analysis and compare against target impedance line.
Iterate: If peaks exceed target, add capacitors, change values, or modify placement. Re-simulate.
Simulation Setup Parameters
Frequency sweep: 100 Hz to 10 GHz (logarithmic, 200 points/decade)
Port configuration: Current sink at IC, Voltage source at VRM
Capacitor models: Include ESR, ESL, and frequency-dependent parameters
Plane mesh: Maximum element size = lambda/20 at highest frequency
At 10 GHz in FR4 (er=4.2): lambda = 14.6mm, mesh size < 0.73mm
Via model: Include via barrel inductance (typically 0.2-1.0nH per via)
Boundary: PEC or radiation boundary at board edges
Interpreting Results
Below target at all frequencies: PASS - PDN design is adequate.
Peak at specific frequency: Identify which cap group transitions cause the peak. Add intermediate values.
High impedance in broad band: Insufficient capacitor quantity or VRM bandwidth too low.
Rising impedance at high frequency: Plane inductance dominant. Need thinner dielectric or more on-die capacitance.
Complete simulation with passing results:
Design: FPGA board, VCCINT = 0.85V, I_max = 20A, Z_target = 1.3 mOhm
Simulation shows:
- DC to 100kHz: 0.8 mOhm (VRM dominant)
- 100kHz to 10MHz: 1.1 mOhm (bulk + mid caps)
- 10MHz to 200MHz: 0.9 mOhm (HF MLCC decoupling)
- 200MHz to 1GHz: 1.2 mOhm (UHF caps + plane capacitance)
All below 1.3 mOhm target. Design approved for fabrication.
No simulation performed - issues found in lab:
Design shipped without PI simulation. In lab testing:
- 150mV ripple measured on 1.0V rail (15% -- specification is 5%)
- Clock jitter increased from 5ps to 45ps due to power supply noise
- Intermittent bit errors in DDR4 interface at high data rates
- Board required 3 respins adding $180K cost and 12 weeks delay
Sigrity PowerSI Workflow:
1. File > Import > ODB++ (or native Allegro .brd)
2. Setup > Power Nets > Select VCC, GND
3. Setup > Ports > Add at IC ball locations
4. Setup > Components > Auto-assign cap models from library
5. Analysis > Impedance > Set frequency range > Run
6. Results > Plot Z vs Freq > Add Target Line
Ansys SIwave Workflow:
1. Import Layout (ODB++, Gerber, .brd)
2. HFSS > PI > Power Integrity Analysis
3. Define Sources (VRM ports) and Sinks (IC ports)
4. Component Library > Map decoupling caps
5. Solve > Frequency Domain (100Hz-10GHz)
6. Results > Z-parameter plot > Compare vs target
HyperLynx PI Workflow:
1. Import layout (HYP, ODB++, or Gerber)
2. PI > PDN Analysis
3. Wizard: Define supply, set target Z
4. Auto-detect decoupling caps from BOM
5. Run Analysis > Review impedance plot
6. Use Optimizer to suggest cap additions
Using ideal capacitor models: Always use vendor SPICE models or measured S-parameters. Ideal models miss ESL and give optimistic results.
Insufficient mesh resolution: Coarse mesh misses plane resonances. Use at least lambda/20 meshing.
Not modeling all vias: Via inductance is significant. Include all power/ground vias in the model.
Simulating only one IC port: Large ICs have many power pins spread across the package. Simulate at multiple locations.
Ignoring manufacturing tolerances: Capacitor values have +/-20% tolerance (X5R). Simulate worst-case with derated values.
