Module 4.1 - Radiated Emissions
Design review checkpoints for controlling unintentional electromagnetic radiation from PCB assemblies and systems
Design review checkpoints for controlling unintentional electromagnetic radiation from PCB assemblies and systems
Every digital clock signal generates harmonics that extend far beyond the fundamental frequency. The spectral envelope of a trapezoidal waveform determines the maximum potential emissions at each harmonic. Estimating this content early in design allows proactive filtering and layout strategies.
A trapezoidal clock waveform with amplitude A, period T, rise time tr, fall time tf, and duty cycle D has a spectral envelope defined by:
Consider a 100 MHz clock with 3.3V amplitude, 50% duty cycle, and 0.5 ns rise time:
Clock: 100 MHz, A = 3.3V, D = 0.5, tr = 0.5 ns
Corner frequencies:
f1 = 1/(pi * 0.5 * 10ns) = 63.7 MHz
f2 = 1/(pi * 0.5ns) = 636.6 MHz
Harmonic amplitudes (envelope):
Fundamental (100 MHz): 20*log10(2*3.3*0.5) = 10.4 dBV
3rd harmonic (300 MHz): 10.4 - 20*log10(3) = 0.9 dBV (flat region)
5th harmonic (500 MHz): 10.4 - 20*log10(5) = -3.6 dBV (flat region)
7th harmonic (700 MHz): 10.4 - 40*log10(700/636.6) = approx -1.3 dBV (-20 dB/decade rolloff begins)
9th harmonic (900 MHz): 10.4 - 20*log10(9) - 20*log10(900/636.6) = -12.5 dBV
FCC Class B limit at 300 MHz (3m): 43.5 dBuV/m
Estimated field from 1cm loop at 300 MHz: needs loop area analysis (see next checkpoint)
100 MHz clock with spread spectrum clocking (SSC): Using a +/-0.5% center-spread modulation at 33 kHz modulation rate reduces peak harmonic amplitude by approximately 7-10 dB. Combined with a 1 ns rise time (instead of minimum 0.5 ns), the second corner frequency drops to 318 MHz, providing additional 20 dB/decade rolloff above that point.
100 MHz clock routed as microstrip on top layer with no series resistance: Fast edge rate (0.3 ns) pushes significant harmonic content to 1 GHz+. Long trace (5 cm) acts as an efficient antenna at 1.5 GHz (quarter-wave). No spread spectrum. Result: 15-20 dB over FCC Class B limit at 300-900 MHz harmonics.
Spectrum Analyzer: Use peak detector mode with 120 kHz RBW (per CISPR 32) for frequencies above 30 MHz. Set span to cover at least up to 10th harmonic of highest clock. Use max-hold trace for 30 seconds minimum to capture worst-case peaks.
HFSS/CST: Import the PCB stackup and trace geometry. Apply a trapezoidal waveform excitation at clock source. Use far-field radiation pattern post-processing to estimate radiated field at test distance (3m or 10m).
Ignoring PLL output harmonics: PLL jitter creates phase noise sidebands that spread harmonic energy. While peak levels may be lower, the broadband noise floor rises, potentially violating quasi-peak limits.
Using typical rise time instead of minimum: Always use the minimum (fastest) rise time from the datasheet for worst-case analysis. Process variations can make actual rise times 30-50% faster than typical.
| Frequency Range | FCC Class B (3m) dBuV/m | CISPR 32 Class B (10m) dBuV/m | CISPR 32 Class A (10m) dBuV/m |
|---|---|---|---|
| 30 - 88 MHz | 40.0 | 30.0 | 40.0 |
| 88 - 216 MHz | 43.5 | 30.0 | 40.0 |
| 216 - 230 MHz | 46.0 | 30.0 | 40.0 |
| 230 - 960 MHz | 46.0 | 37.0 | 47.0 |
| 960 MHz - 1 GHz | 54.0 | 37.0 | 47.0 |
| Above 1 GHz | 54.0 | 37.0 | 47.0 |
Current loops are the primary radiation mechanism for PCB-level emissions. The radiated electric field from a small current loop is directly proportional to the loop area, the current magnitude, and the square of the frequency. Minimizing loop area is the single most effective technique for reducing radiated emissions.
Signal: 100 MHz clock, 3.3V LVCMOS, Z0 = 50 ohm
Current: I = 3.3V / 50 ohm = 66 mA = 0.066 A
Trace length: 5 cm = 0.05 m
Dielectric height (microstrip): 0.2 mm = 0.0002 m
Loop area: A = 0.05 * 0.0002 = 10 * 10^-6 m^2
At 3rd harmonic (300 MHz = 3*10^8 Hz):
E = 1.316e-14 * (3e8)^2 * 10e-6 * 0.066 / 3
E = 1.316e-14 * 9e16 * 10e-6 * 0.066 / 3
E = 1.316e-14 * 9e16 * 6.6e-7 / 3
E = 2.61e-4 V/m = 261 uV/m = 48.3 dBuV/m
CISPR 32 Class B limit at 300 MHz (10m): 37 dBuV/m
RESULT: 11.3 dB OVER LIMIT -- FAILS!
Mitigation: Move to stripline (inner layer) with 0.1 mm dielectric:
New area: 0.05 * 0.0001 = 5 * 10^-6 m^2
New E = 24.2 dBuV/m (within limit with 12.8 dB margin)
DDR3 clock routed on inner stripline layer: Layer 3 (signal) referenced to Layer 2 (ground) with 4 mil dielectric spacing. 2-inch trace creates loop area of only 2 * 0.0254 * 0.0001 = 5.08e-6 m^2. Continuous reference plane beneath with no splits, vias, or cutouts under the trace. Radiated emission at 800 MHz (fundamental) is 12 dB below Class B limit.
DDR3 clock on outer layer crossing power plane split: Layer 1 microstrip with 8 mil height, crossing a split in the Layer 2 ground plane. Return current must detour around the split, adding 1 cm x 8 mil = 2.03e-5 m^2 extra loop area. Total effective loop area increases by 4x, adding 12 dB to radiated emissions. The 400 MHz harmonic exceeds the limit by 8 dB.
EMScan/Near-Field Scanner: Use a near-field probe (H-field loop) to scan over the PCB surface. Hot spots indicate large loop areas. Frequency-selective measurement at clock harmonics identifies the dominant radiating loops. Map the H-field at 5mm above the board surface with 1mm resolution.
CST Studio Suite: Import PCB geometry from ODB++ or Gerber. Set up a transient co-simulation with circuit-level drivers. Use the far-field probe at 3m/10m distance to calculate radiated field. Overlay the surface current distribution to identify dominant current loops.
Via transitions without stitching: When a signal transitions from Layer 1 (ref: Layer 2 GND) to Layer 4 (ref: Layer 5 GND), the return current must also transition. Without a nearby ground stitching via (within 50 mil), the return current loop area at the via transition can be very large, creating a significant radiation source.
Ignoring displacement current loops: Even without a galvanic return path, displacement current flows through parasitic capacitances, creating loops. This is particularly important for signals with no continuous reference plane.
The edges of PCB power and ground planes act as slot antennas that radiate electromagnetic energy. This edge radiation is driven by the voltage between the planes (caused by switching noise) and is most significant when the board dimension approaches a half-wavelength at the frequency of interest.
Board: 150mm x 100mm, FR4 (er = 4.3), 0.2mm dielectric between power/ground planes
Cavity resonances:
f_10 = (3e8/2) * (1/0.15) / sqrt(4.3) = 482 MHz
f_01 = (3e8/2) * (1/0.10) / sqrt(4.3) = 723 MHz
f_11 = (3e8/2) * sqrt((1/0.15)^2 + (1/0.10)^2) / sqrt(4.3) = 869 MHz
If 100 MHz clock has 5th harmonic at 500 MHz:
Close to f_10 = 482 MHz -- potential resonance coupling!
Plane voltage at resonance can be 10-100x the DC ripple
Mitigation: Via stitching at board edge
At 500 MHz: lambda = 600mm / sqrt(4.3) = 289mm
Via spacing = lambda/20 = 14.5 mm
Place ground stitching vias every 14 mm around the perimeter.
Board with proper edge treatment: Ground stitching vias placed every 10 mm around entire board perimeter, power plane pulled back 60 mil (20H with 3 mil dielectric), additional decoupling capacitors (100 pF) placed at 15 mm spacing along edges with high-speed signal routing. Near-field scan shows 15 dB reduction in edge radiation at 500 MHz compared to untreated design.
Board with power plane extending to edges: Power plane reaches all four board edges with no setback. No stitching vias along edges. A 125 MHz oscillator harmonic at 500 MHz coincides with the board's f_10 cavity resonance. Edge radiation at 500 MHz is 22 dB above CISPR 32 Class B limit. The entire edge acts as a slot antenna.
Forgetting about higher-order modes: Even if the fundamental resonance is above your clock frequency, higher harmonics of lower-frequency clocks can still excite board resonances.
Stitching via spacing too large: Vias must be spaced at lambda/20 of the highest frequency of concern. At 1 GHz with FR4, lambda = 145 mm, so spacing must be less than 7.25 mm.
Heatsinks attached to ICs can act as antennas when coupled to the switching noise of the die through parasitic capacitance. The heatsink fin structure can resonate at specific frequencies, creating efficient radiation at those points.
FPGA heatsink with multi-point grounding: Heatsink base grounded to PCB ground plane through 4 spring-loaded contact pins at the corners, providing less than 1 nH inductance connection at each point. Thermal interface material (TIM) is electrically conductive (graphite pad). Heatsink resonance at 1.2 GHz is effectively damped. No radiation peak observed at heatsink resonant frequency.
Processor heatsink floating (no ground connection): Heatsink attached with non-conductive thermal paste, electrically floating. Parasitic capacitance of 8 pF to die. At 500 MHz clock harmonic: I_coupled = 3.3V * 2*pi*500e6 * 8e-12 = 83 uA. With 40mm fin acting as quarter-wave monopole at 1.875 GHz, radiation peak at that frequency is 12 dB over limit.
Near-field probe (EMScan): Use an E-field probe positioned 5mm above heatsink fins while system operates. Sweep 30 MHz to 3 GHz. Look for narrowband peaks that correspond to heatsink resonances (verify by removing heatsink -- peaks should disappear).
HFSS simulation: Model the heatsink geometry, IC package, and PCB ground plane. Add a lumped capacitance between die and heatsink. Run eigenmode analysis to find resonant frequencies, then driven simulation to predict far-field radiation.
Cables attached to electronic systems are typically the dominant radiation mechanism, far exceeding PCB radiation. Even small common-mode currents on cables produce significant radiated fields because cable lengths are often comparable to wavelengths at frequencies of concern. As little as 5 uA of common-mode current on a 1m cable can cause FCC Class B failure.
| Frequency | FCC B Limit (3m) | Max I_cm (1m cable) | Max I_cm (2m cable) |
|---|---|---|---|
| 30 MHz | 40.0 dBuV/m | 8.0 uA | 4.0 uA |
| 100 MHz | 43.5 dBuV/m | 7.2 uA | 3.6 uA |
| 200 MHz | 43.5 dBuV/m | 3.6 uA | 1.8 uA |
| 500 MHz | 46.0 dBuV/m | 1.9 uA | 0.95 uA |
| 1000 MHz | 54.0 dBuV/m | 1.5 uA | 0.75 uA |
USB cable with proper CM filtering: Common-mode choke (Murata DLW21SN900HQ2) placed within 5 mm of USB connector. Impedance: 90 ohm at 100 MHz, 200 ohm at 500 MHz. Shield bonded 360 degrees to connector shell which connects directly to chassis ground. Common-mode current measured at 2.1 uA at 480 MHz (USB harmonic). 8 dB below required limit.
USB cable with pigtail shield termination: Cable shield connected via 25mm wire pigtail to PCB ground. At 500 MHz, this pigtail has inductance of 25 nH (impedance = 78 ohm), allowing most CM current to pass through. Measured CM current: 18 uA at 480 MHz. Fails FCC Class B by 19 dB.
Assuming shielded cable solves the problem: A shielded cable with poor termination can be WORSE than an unshielded cable, because the shield acts as an antenna while providing no filtering to the inner conductors.
Filtering only differential mode: Most radiated emission problems are caused by common-mode currents. Differential-mode filters (series resistors, capacitors to ground) do not reduce common-mode emissions. You need common-mode chokes or balanced filtering.
The final check combines all radiation mechanisms and compares the estimated total spectral content against regulatory limits with appropriate design margin. A minimum of 6 dB margin is required for design confidence; 10 dB margin is recommended for production variability.
Comprehensive margin analysis spreadsheet: All 24 clock harmonics (from 6 oscillators) tabulated with estimated radiated field. Cable CM contributions added. Board edge contribution added. Total compared to limit. All points show greater than 8 dB margin. Worst case: 480 MHz USB harmonic at 8.2 dB margin (28.8 dBuV/m estimated vs. 37.0 dBuV/m limit).
No margin analysis performed - rely on test only: Design proceeds to prototype without any emission estimation. First pre-compliance test shows 5 frequencies failing by 10-20 dB. Board redesign required (add 6 weeks to schedule). Cost: re-spin PCB + re-layout + second pre-compliance test = $50,000+ and 2 months delay.
Spectrum Analyzer Setup for Pre-Compliance: