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Module 4.2 - Conducted Emissions

Design review checkpoints for controlling noise conducted back to the AC mains or DC power bus through the power input

4.2.1 SMPS Switching Harmonics Filtered Critical

Switch-mode power supplies generate conducted emissions at the switching frequency and its harmonics. The fundamental switching frequency typically falls in the 50 kHz to 2 MHz range, with harmonics extending to 30 MHz and beyond. These harmonics propagate back through the power input and must be attenuated below regulatory limits.

SMPS Emission Mechanisms

Differential-mode (DM) noise:
- Caused by pulsating input current drawn by the switching converter
- Fundamental amplitude: I_dm = I_out * D * (1-D) / (sqrt(2) * ripple_factor)
- For buck converter: I_dm_peak = delta_IL = (Vin-Vout)*D*T/L

Common-mode (CM) noise:
- Caused by dV/dt on switching node coupling through parasitic capacitance to ground
- I_cm = C_parasitic * dV/dt
- Typical C_parasitic: 5-50 pF (MOSFET drain to heatsink/chassis)

For 500 kHz switching, 12V to 3.3V buck, L = 4.7 uH:
D = 3.3/12 = 0.275
delta_IL = (12-3.3)*0.275*(1/500e3)/4.7e-6 = 1.02 A peak-to-peak ripple
DM noise voltage across 50 ohm LISN: V_dm = 1.02/2 * 50 = 25.5 V = 148 dBuV!

Step-by-Step Procedure

  1. Identify all switching converters in the system: type (buck/boost/flyback/forward), switching frequency, input voltage range, output power.
  2. Calculate the input current ripple waveform for each converter at maximum load.
  3. Determine the spectral envelope of the switching current (trapezoidal approximation with switching rise/fall times).
  4. Estimate the common-mode current from parasitic capacitance and switching dV/dt.
  5. Calculate required filter attenuation at each harmonic to meet limits with 6 dB margin.
  6. Design input filter (LC or Pi topology) to provide required attenuation without compromising converter stability.

Conducted Emission Limits

Frequency RangeCISPR 32 Class B QP (dBuV)CISPR 32 Class B Avg (dBuV)FCC Class B (dBuV)
150 kHz - 500 kHz66 to 56 (linear decrease)56 to 46 (linear decrease)66 to 56
500 kHz - 5 MHz564656
5 MHz - 30 MHz605060

Note: CISPR 32 limits are measured at LISN output (50 ohm/50 uH). FCC Part 15 uses similar LISN setup.

500 kHz buck converter with designed EMI filter: Two-stage LC filter: Stage 1 (closest to converter): L1=10uH, C1=1uF X7R ceramic. Stage 2 (closest to input): L2=47uH, C2=4.7uF ceramic + 100nF. Provides 80 dB attenuation at 500 kHz (switching fundamental). Common-mode choke (10mH) between stages handles CM noise. Result: All harmonics 10+ dB below Class B limits.

500 kHz buck converter with only bulk input capacitor: Single 47 uF electrolytic at input. ESR = 0.2 ohm, ESL = 5 nH. At 500 kHz, impedance is dominated by ESL: Z = 2*pi*500e3*5e-9 = 15.7 mohm (but ESR dominates = 0.2 ohm). Minimal filtering. First harmonic at 500 kHz: 148 - 20*log10(attenuation) = still 120+ dBuV at LISN. Fails by 64 dB!

Filter stability interaction: Adding an input LC filter creates a resonance that can destabilize the converter. The filter output impedance must be less than the converter input impedance at all frequencies. Use Middlebrook's criterion: Z_filter_out < Z_converter_in. Add damping resistor in series with a capacitor across the filter inductor.

Electrolytic capacitor limitations: Above 100 kHz, electrolytic capacitors are essentially resistive (ESR-dominated) and provide no filtering. Always parallel with low-ESR ceramics for high-frequency filtering.

4.2.2 Input Filter Design (LISN Compatible) Critical

The input EMI filter must be designed to work correctly with the Line Impedance Stabilization Network (LISN) used during conducted emission testing. The LISN presents a defined source impedance (50 ohm || 50 uH) to the equipment under test, and the filter must provide adequate attenuation as seen from this source.

LISN Equivalent Circuit

Standard LISN (per CISPR 16-1-2):
- 50 uH inductor in series with the mains line
- 50 ohm resistor from line to ground (measurement port)
- 1 uF capacitor in series with 50 ohm (AC coupling to receiver)
- 0.25 uF across the mains (L to N)

LISN impedance seen by EUT:
Z_LISN = 50 ohm || j*2*pi*f*50e-6
At 150 kHz: Z = 50 || j47.1 = 24.3 ohm at 43.3 degrees
At 500 kHz: Z = 50 || j157 = 47.6 ohm at 17.6 degrees
At 5 MHz: Z = 50 || j1571 = 49.9 ohm at 1.8 degrees
Above ~500 kHz, LISN appears as pure 50 ohm resistive

Pi-Filter Design Procedure

  1. Determine required attenuation: A_req = Noise_level - Limit + Margin (in dB). Example: 148 dBuV - 56 dBuV + 6 dB = 98 dB at 500 kHz.
  2. Select filter topology: LC (2nd order, 40 dB/decade), Pi (3rd order, 60 dB/decade), or two-stage LC (4th order, 80 dB/decade).
  3. For Pi-filter: Choose corner frequency. For 98 dB at 500 kHz with 60 dB/decade: f_c = 500 kHz * 10^(-98/60) = not achievable with single-stage Pi at 60 dB/dec -- need two-stage.
  4. For two-stage LC: Each stage provides 40 dB/decade. Need 98 dB at 500 kHz. Corner frequency: f_c = 500 kHz / 10^(98/80) = 500 kHz / 83.2 = 6.0 kHz.
  5. Calculate component values: L = Z_source / (2*pi*f_c) = 50 / (2*pi*6000) = 1.33 mH per stage, C = 1/(2*pi*f_c*Z_load) = 1/(2*pi*6000*50) = 0.53 uF per stage.
  6. Verify filter does not resonate at any switching harmonic. Add damping as needed.
  7. Check that filter capacitor RMS current rating is adequate for the switching ripple current.

Component Selection

Two-stage DM filter for 500 kHz SMPS, 12V/5A input:

Stage 1 (converter side):
  L1 = 10 uH (Wurth 744770110, I_sat = 6A, DCR = 15 mohm)
  C1 = 2.2 uF X7R ceramic (TDK C3225X7R1H225K, 50V, ESR = 5 mohm)
  f_c1 = 1/(2*pi*sqrt(10e-6 * 2.2e-6)) = 33.9 kHz
  Attenuation at 500 kHz: 40*log10(500/33.9) = 46.4 dB

Stage 2 (input side):
  L2 = 47 uH (Wurth 744770147, I_sat = 5.5A, DCR = 35 mohm)
  C2 = 4.7 uF X7R ceramic (TDK C3225X7R1E475K, 25V, ESR = 3 mohm)
  f_c2 = 1/(2*pi*sqrt(47e-6 * 4.7e-6)) = 10.7 kHz
  Attenuation at 500 kHz: 40*log10(500/10.7) = 66.8 dB

Total attenuation at 500 kHz: 46.4 + 66.8 = 113.2 dB
Noise at LISN: 148 - 113.2 = 34.8 dBuV (limit: 56 dBuV)
Margin: 21.2 dB -- PASSES with excellent margin

Damping: 1 ohm resistor in series with 10 uF across L2 to prevent resonance
            

Properly damped two-stage filter: Two LC stages with staggered corner frequencies (10 kHz and 30 kHz) to avoid resonance stacking. Each inductor has a parallel RC snubber (1 ohm + 10 uF) to damp the LC resonance Q. Input impedance remains low and flat from DC to 100 kHz, ensuring converter stability. Total insertion loss measured: 95 dB at 500 kHz, 110 dB at 1 MHz.

Undamped single-stage LC with high-Q resonance: Single 100 uH + 10 uF LC filter with no damping. Resonance at 5 kHz with Q = 50 creates 34 dB gain peak. Converter becomes unstable (oscillates at 5 kHz). Also, above resonance the inductor self-resonant frequency (SRF = 2 MHz) causes filter to become ineffective above 2 MHz, missing harmonics at 2.5 and 3 MHz.

LISN Measurement Setup:

  • LISN must warm up 30 minutes before measurement
  • Connect LISN measurement port to spectrum analyzer via 50-ohm cable
  • Terminate unused LISN port with 50-ohm load
  • Ground LISN to reference ground plane with short, wide strap
  • EUT power cord length: 1m maximum between LISN and EUT
  • Verify LISN calibration: inject known signal, verify correct reading

4.2.3 Common-Mode Current Path Identified Critical

Common-mode (CM) conducted emissions are typically the dominant emission mechanism above 1 MHz. CM currents flow equally on both power lines (L and N) and return through the ground/earth conductor or parasitic capacitance to ground. Identifying and controlling these paths is essential for conducted emission compliance.

Common-Mode Current Sources in SMPS

Primary CM current sources:

1. MOSFET drain to heatsink/chassis:
I_cm1 = C_dh * dV_drain/dt
C_dh = 5-20 pF (typical TO-220 to heatsink)
dV/dt = 400V / 50ns = 8 V/ns for offline SMPS
I_cm1 = 10pF * 8e9 = 80 mA peak!

2. Transformer interwinding capacitance:
I_cm2 = C_pw * dV_primary/dt
C_pw = 10-100 pF (typical transformer)

3. PCB trace-to-chassis capacitance:
I_cm3 = C_trace * dV_node/dt
Typically 0.5-5 pF per cm^2 of copper

Total CM current: I_cm = I_cm1 + I_cm2 + I_cm3 (vector sum)

Step-by-Step Identification

  1. Map all switching nodes (high dV/dt) in the power supply schematic.
  2. Identify parasitic capacitances from each switching node to chassis/earth ground (heatsink mounting, transformer interwinding, PCB layout).
  3. Calculate CM current magnitude at the switching frequency: I_cm = sum(C_parasitic * dV/dt).
  4. Trace the CM current return path: from chassis ground, through earth conductor, through LISN, back to power input.
  5. Determine the CM voltage at the LISN: V_cm = I_cm * Z_LISN/2 (factor of 2 because CM current splits between L and N).
  6. Design Y-capacitors and CM chokes to divert/block CM current before it reaches the power input.

Flyback converter with controlled CM path: MOSFET heatsink isolated with 1.5 mm thick alumina washer (C = 3 pF) instead of mica (C = 15 pF). Faraday shield between transformer primary and secondary windings reduces interwinding capacitance from 50 pF to 5 pF. Y-capacitors (2x 2.2 nF, Class Y2) placed symmetrically from L and N to chassis. CM choke (10 mH) at input. Result: CM emissions 12 dB below Class B limit.

Flyback with no CM attention: MOSFET mounted directly to metal chassis (C = 100 pF). No Faraday shield in transformer. Single 4.7 nF Y-cap from one line only (asymmetric). No CM choke. dV/dt at drain = 10 V/ns. CM current: 100pF * 10e9 = 1A peak! Even at 50% duty: CM harmonic at 100 kHz = 400 mA peak = 152 dBuV at LISN. Fails by 96 dB at fundamental!

Y-capacitor safety limits: Y-capacitors from line to earth must be limited for safety (touch current): max 4.7 nF for Class Y2 (medical: 470 pF for Class Y1). This limits CM filtering capability - cannot simply add more capacitance.

CM and DM interaction: Y-capacitor imbalance converts CM noise to DM noise and vice versa. Always use matched pairs of Y-caps (from same lot) placed symmetrically.

4.2.4 Differential-Mode Filter Sized Major

Differential-mode (DM) noise flows between the power lines (L to N) and is caused by the pulsating input current of switching converters. DM noise typically dominates below 500 kHz to 2 MHz, while CM noise dominates at higher frequencies. The DM filter uses X-class capacitors and series inductors.

DM Filter Design

DM noise source: Switching current ripple in input capacitor ESR/ESL

For a buck converter:
I_ripple(f_sw) = delta_IL * sqrt(D*(1-D)) = continuous conduction mode
V_dm_at_LISN = I_ripple * Z_LISN_DM = I_ripple * 25 ohm (each LISN is 50 ohm)

For boost/flyback (discontinuous input current):
I_ripple(f_sw) = I_out * D / (1-D) (fundamental component)
Much higher DM noise than buck converters!

Required DM attenuation:
A_dm = V_noise_at_LISN(dBuV) - Limit(dBuV) + Margin(dB)

DM filter corner frequency:
f_c = f_sw / 10^(A_dm / (N*20)) where N = filter order
For 2nd order (single LC): f_c = f_sw / 10^(A_dm/40)
For 4th order (two-stage LC): f_c = f_sw / 10^(A_dm/80)

X-Capacitor Selection

X-capacitor classes (per IEC 60384-14):
  Class X1: 4 kV peak pulse rating, for C_across-the-line after mains filter
  Class X2: 2.5 kV peak pulse, for general across-the-line use (most common)
  Class X3: 1.2 kV peak pulse, for general applications

Typical X2 capacitor values and SRF:
  100 nF film: SRF ~ 15-20 MHz (useful to 10 MHz)
  470 nF film: SRF ~ 5-8 MHz
  1 uF film: SRF ~ 3-5 MHz
  2.2 uF film: SRF ~ 2-3 MHz

For ceramic X-capacitors (higher SRF but lower capacitance):
  100 nF C0G/NP0: SRF ~ 50-100 MHz
  1 uF X7R: SRF ~ 10-20 MHz

Design rule: Place both film and ceramic X-caps in parallel:
  Film (1 uF) for low-frequency DM filtering (150 kHz - 2 MHz)
  Ceramic (100 nF) for high-frequency DM filtering (2 MHz - 30 MHz)
            

Boost PFC with proper DM filter: 65 kHz boost PFC converter, 400W, AC input. DM filter: Stage 1: 330 uH inductor (amorphous core, I_sat = 5A) + 2x 470 nF X2 film capacitors. Stage 2: leakage inductance of CM choke (50 uH) + 1 uF X2 film + 100 nF C0G ceramic. Corner frequency: 13 kHz. Provides 72 dB at 150 kHz (fundamental). Total system DM emissions: 42 dBuV at 150 kHz (limit: 66 dBuV QP). 24 dB margin.

Boost PFC with inadequate DM filter: Only the PFC inductor (150 uH) and a 100 nF X2 cap at input. Corner frequency: 41 kHz. Attenuation at 150 kHz: only 40*log10(150/41) = 22.6 dB. DM noise from discontinuous boost input current is 130 dBuV. Result: 130 - 22.6 = 107.4 dBuV at LISN. Limit: 66 dBuV. Fails by 41.4 dB!

4.2.5 Pi-Filter Corner Frequency Set Major

The EMI filter corner frequency determines the frequency above which attenuation begins. Setting this correctly requires balancing between adequate attenuation at the lowest emission frequency (150 kHz for CISPR, or switching frequency) and practical component values/sizes. Too low a corner frequency requires impractically large inductors.

Corner Frequency Selection Methodology

Pi-filter transfer function:
H(s) = 1 / (1 + s*(C1+C2)*R_s + s^2*L*(C1+C2) + s^3*L*C1*C2*R_s)

Simplified (assuming R_s = 50 ohm LISN):
For C1 = C2 = C, the corner frequency:
f_c = 1 / (2*pi*sqrt(L*C)) (for each LC section)

Attenuation above corner frequency:
Pi-filter: 60 dB/decade (3rd order)
T-filter (dual inductor): 60 dB/decade
Double-Pi: 100 dB/decade (5th order) -- but beware resonances

Practical corner frequency range:
- AC mains (150 kHz start): f_c = 5-30 kHz typical
- 48V DC bus (CISPR 32): f_c = 10-50 kHz typical
- 12V/5V DC (CISPR 32): f_c = 20-100 kHz typical

Design Trade-offs

Corner FreqInductor SizeCapacitor SizeAtten @ 150kHzAtten @ 500kHz
5 kHz1-10 mH (large)10-100 uF88 dB120 dB
10 kHz0.5-2 mH2-10 uF70 dB102 dB
20 kHz100-500 uH1-5 uF52 dB84 dB
50 kHz50-200 uH0.1-1 uF28 dB60 dB

Correctly sized Pi-filter for 200 kHz SMPS: Target: 80 dB at 200 kHz (switching fundamental). Pi-filter with f_c = 10 kHz: L = 1 mH (Wurth 744821001), C1 = C2 = 2.2 uF (X2 film). Attenuation at 200 kHz: 60*log10(200/10) = 78 dB. With 6 dB margin target met. Physical size: inductor 20x20x15mm, capacitors 18x7x12mm each. Total filter volume: 15 cm^3 -- acceptable for 200W supply.

Corner frequency too close to switching frequency: 200 kHz SMPS with f_c = 100 kHz. Attenuation at 200 kHz (first harmonic): only 60*log10(200/100) = 18 dB. Required: 80 dB. Insufficient by 62 dB. Designer would need to drop corner to 10 kHz, requiring 10x larger inductor -- should have been planned from the start to reserve board space.

Inductor saturation at rated current: EMI filter inductors must maintain inductance at the DC bias current. Iron powder cores lose 50-80% of inductance at rated current. Use inductance value at actual operating current, not the zero-bias value. Amorphous or nanocrystalline cores maintain inductance better but cost more.

Capacitor derating with DC bias (ceramics): X7R ceramic capacitors lose 50-80% of capacitance at rated voltage. A "4.7 uF" X7R at 80% of rated voltage may only provide 1.5 uF actual capacitance. Film capacitors do not have this issue.

4.2.6 Conducted Emission Pre-Scan Recommended Minor

A conducted emission pre-scan early in development verifies that the EMI filter design is effective before committing to final hardware. Pre-compliance measurement using a LISN and spectrum analyzer identifies problems while corrections are still inexpensive.

Pre-Scan Test Setup

Equipment required:
- LISN (50 uH / 50 ohm, per CISPR 16-1-2)
- Spectrum analyzer or EMI receiver (9 kHz - 30 MHz minimum)
- 50-ohm coaxial cable (double-shielded RG-223 or RG-142)
- 50-ohm termination for unused LISN port
- Ground reference plane (min 2m x 2m copper/aluminum sheet)

Measurement conditions:
- EUT operating at maximum load / worst-case mode
- Power cord length: 1m between LISN and EUT
- EUT 40 cm above reference ground plane
- LISN bonded to reference ground plane
- Ambient temperature: 23 +/- 5 degrees C
- Measure BOTH lines (L and N) separately

Pre-Scan Procedure

  1. Set up test environment per the diagram above. Verify ground reference plane connections.
  2. Calibrate: Remove EUT, inject known signal at LISN EUT port, verify spectrum analyzer reads correct level (account for cable loss).
  3. Connect EUT, power on at maximum load.
  4. Perform peak detector scan: 150 kHz to 30 MHz, RBW = 9 kHz (CISPR Band B), sweep time = auto.
  5. Identify all peaks within 20 dB of the limit line. These are potential failures.
  6. For peaks within 10 dB of limit: switch to quasi-peak detector and measure at those specific frequencies.
  7. Document results with screenshots showing both peak and QP measurements overlaid with limit line.
  8. If peaks are above limit: diagnose using CM/DM separation technique (measure L+N and L-N to separate CM and DM components).

CM/DM Noise Separation

To separate CM and DM components, measure at both LISN ports:

V_L = voltage at Line LISN port
V_N = voltage at Neutral LISN port

V_CM = (V_L + V_N) / 2  (common-mode component)
V_DM = (V_L - V_N) / 2  (differential-mode component)

Practical method using two LISNs simultaneously:
1. Connect both LISNs to spectrum analyzer (use power splitter/combiner)
2. In-phase combination (0 degree): gives V_L + V_N = 2*V_CM
3. Anti-phase combination (180 degree via balun): gives V_L - V_N = 2*V_DM

Alternative: Commercial CM/DM separation networks (e.g., Schwarzbeck CMDM 8700)

If V_CM dominates: Improve CM choke, reduce parasitic capacitance, add Y-caps
If V_DM dominates: Improve DM filter (add inductance or X-capacitance)
            

Pre-scan at EVT stage identifies filter gap: Pre-compliance scan shows 3rd and 5th harmonics of 300 kHz switching (900 kHz and 1.5 MHz) are 4 dB and 2 dB above Class B QP limit respectively. CM/DM separation reveals DM dominance. Solution: Add 100 nF X2 capacitor at filter output (cost: $0.05, board space reserved). Re-scan shows 8 dB margin. Fix implemented before DVT build with zero schedule impact.

No pre-scan, first test at compliance lab: Product sent directly to accredited lab for conducted emission test. Fails at 5 frequencies, requiring board redesign to add filter components for which no space was allocated. Re-layout, re-fabrication, and re-test costs $35,000 and delays program by 6 weeks. A $2,000 pre-scan investment would have caught this at the prototype stage.

Spectrum Analyzer Settings for Conducted Pre-Scan:

  • Frequency: 9 kHz to 30 MHz (start at 9 kHz to see below-band noise floor)
  • RBW: 9 kHz (CISPR Band B, 150 kHz - 30 MHz)
  • VBW: 3x RBW minimum (27 kHz) or use auto
  • Detector: Peak for initial scan, Quasi-Peak for compliance comparison
  • Reference level: 100 dBuV
  • Display units: dBuV (NOT dBm; convert: dBuV = dBm + 107 for 50 ohm)
  • Trace: Max-hold for 2 complete measurement sweeps minimum
  • Apply LISN transducer factor if not unity (most 50-ohm LISNs have 0 dB factor)