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Module 4.3 - Susceptibility & Immunity

Design review checkpoints for ensuring product immunity to external electromagnetic disturbances per IEC 61000-4-x standards

4.3.1 ESD Immunity Designed (IEC 61000-4-2) Critical

Electrostatic discharge (ESD) is one of the most common causes of field failures and compliance test failures. The IEC 61000-4-2 standard defines test levels and methods for contact and air discharge to all accessible points. Design-level ESD protection must be incorporated from the beginning, as retrofitting is extremely difficult.

IEC 61000-4-2 Test Levels

LevelContact Discharge (kV)Air Discharge (kV)Typical Application
122Light industrial, protected environment
244Residential, commercial
368Industrial
4815Heavy industrial, harsh environments
Special>8>15As specified (automotive: 25 kV air)

ESD Waveform Characteristics

Contact discharge waveform (per IEC 61000-4-2):
- Rise time: 0.7 - 1 ns
- Peak current (Level 4, 8 kV): 30 A
- Current at 30 ns: 16 A
- Current at 60 ns: 8 A
- Spectral content extends to > 1 GHz (due to sub-ns rise time)

Energy in ESD pulse:
E = 0.5 * C_body * V^2 = 0.5 * 150pF * (8000)^2 = 4.8 mJ

Peak power: P = I_peak * V_clamp
For 8 kV into TVS with V_clamp = 12V: P = 30A * 12V = 360W (1 ns pulse)

Step-by-Step Design Procedure

  1. Identify all accessible points: connectors, buttons, switches, USB ports, SD card slots, metal enclosure parts, screws, display edges.
  2. Determine the required test level based on product environment (residential = Level 2/3, industrial = Level 3/4).
  3. Design the primary ESD current path: provide a low-impedance path from discharge point to ground that bypasses sensitive electronics.
  4. Select ESD protection devices for each exposed signal line: TVS diodes, varistors, or spark gaps sized for the required clamping voltage and peak current.
  5. Layout the protection components: place within 5 mm of the connector, with wide traces (40+ mil) directly to ground plane. No vias between TVS and connector pin if possible.
  6. Verify with ESD gun test at prototype stage: apply +/- at all accessible points, both contact and air discharge.

Protection Circuit Design

Example: USB 2.0 port ESD protection (Level 4: +/- 8 kV contact)

Requirements:
  - Data rate: 480 Mbps (USB 2.0 High-Speed)
  - Signal voltage: 0 - 3.3V
  - Max capacitance on D+/D-: 2.5 pF (to maintain signal integrity)
  - Clamping voltage: < 10V (below IC absolute max rating)
  - Peak current handling: 30A (1 ns pulse)

Selected device: Nexperia PESD5V0C2BT (dual-channel TVS)
  - Working voltage: 5V
  - Clamping voltage at 16A: 9.8V
  - Capacitance: 0.35 pF per line
  - Package: SOT-23 (small footprint, short leads)

Layout rules:
  1. Place TVS within 3mm of USB connector pins
  2. Ground pad connects directly to ground plane with 4 vias (0.3mm drill)
  3. No series resistance between connector and TVS (would increase voltage at IC)
  4. Series resistance (22 ohm) AFTER TVS to limit current to IC
  5. Keep ESD trace away from sensitive analog signals (min 50 mil spacing)
            

USB port with proper ESD design: TVS array (PESD5V0C2BT) placed 2mm from connector pins on outer PCB layer. Ground connection via 4 x 0.3mm vias directly to solid ground plane. 22 ohm series resistor after TVS for additional current limiting. USB controller has internal ESD (2 kV HBM) as backup. Chassis shell grounded to PCB ground at connector mounting tabs. System passes +/- 8 kV contact, +/- 15 kV air with Criterion A (no degradation).

USB port with TVS placed 20mm from connector: TVS array placed near the USB controller IC instead of at the connector. 20mm trace from connector to TVS has inductance of approximately 20 nH. During 30A ESD pulse: V_trace = L * di/dt = 20nH * 30A/1ns = 600V appears at connector before TVS can respond. IC input sees 600V spike for 1 ns -- causes latch-up or permanent damage despite TVS being present.

Ignoring indirect discharge paths: ESD current flows through the lowest impedance path. A discharge to a metal screw on the enclosure can couple through the chassis, through mounting screws to the PCB, and into ground plane -- causing ground bounce that upsets every IC on the board. Design chassis-to-PCB ground connections to handle this current.

TVS capacitance on high-speed lines: Standard TVS diodes have 5-50 pF capacitance, which destroys signal integrity on USB 3.0, HDMI, PCIe. Use low-capacitance arrays (< 0.5 pF) such as Nexperia PESD or Semtech RClamp series for high-speed interfaces.

ESD Gun Testing: Use a calibrated ESD simulator (Noiseken ESS-2000, Schaffner NSG 438). Perform contact discharge at all metallic points and air discharge at all non-metallic accessible surfaces. Apply 10 discharges at each polarity with 1 second between pulses. Monitor system function during and after test. Document any upsets, resets, or damage.

4.3.2 Radiated Immunity Margin (IEC 61000-4-3) Major

Products must operate correctly in the presence of external RF fields from radio transmitters, cell phones, walkie-talkies, and other intentional radiators. IEC 61000-4-3 defines test methods and levels for radiated RF immunity from 80 MHz to 6 GHz.

IEC 61000-4-3 Test Levels

LevelField Strength (V/m)Typical Application
11Low RF environment (shielded room)
23Residential, commercial, light industry
310Industrial, proximity to transmitters
430Heavy industrial, broadcast stations nearby
SpecialAs specifiedAutomotive (100-200 V/m), Military (50-200 V/m)

Induced Voltage Calculation

Voltage induced on a PCB trace by external RF field:

For a trace of length L acting as a receiving antenna:
V_induced = E * L_eff * (lambda/(4*pi*r)) -- for far-field source

Simplified (trace shorter than lambda/4):
V_induced = E * h * L * 2*pi*f / c
Where h = trace height above ground plane, L = trace length

Example: 10 V/m field at 900 MHz, trace L = 5 cm, h = 0.2 mm (microstrip):
V_induced = 10 * 0.0002 * 0.05 * 2*pi*900e6 / 3e8 = 1.88 mV

For cable (L = 1m, h = 5cm from ground):
V_induced = 10 * 0.05 * 1.0 * 2*pi*900e6 / 3e8 = 942 mV!

This 942 mV on a cable can easily upset sensitive analog circuits or
cause demodulation in RF detector-like junctions (EMI rectification).

Design Strategies for Radiated Immunity

  1. Minimize trace/cable antenna effectiveness: use ground planes under all traces, shield cables, minimize loop areas.
  2. Add RF filtering at all I/O connectors: low-pass filters with corner frequency well below the immunity test start frequency (80 MHz). Typical: 10 MHz filter on analog inputs, 50 MHz on digital.
  3. Use bypass capacitors for RF decoupling: 100 pF - 1 nF ceramic caps close to IC pins on analog inputs. These short RF energy to ground before it enters the IC.
  4. Prevent RF rectification: Add RF bypass caps (100 pF) at the input of every op-amp. Place ferrite beads on high-impedance analog signal paths.
  5. Ensure shielding integrity: metal enclosures with proper seam design, filtered cable penetrations, no unintended apertures.
  6. Validate with pre-compliance RF immunity test using a TEM cell or GTEM cell for bench-level testing.

Sensor analog front-end with RF immunity: Thermocouple input with 100 pF C0G capacitor at connector pin to ground (before any amplification). Ferrite bead (1 kohm at 100 MHz) in series with signal path. Common-mode choke on sensor cable at board entry. Op-amp input has 100 pF feedback cap (limits bandwidth to 1 MHz). Result: No measurable offset shift at 10 V/m from 80 MHz to 2.7 GHz.

High-impedance analog input with no RF filtering: 10 kohm source impedance sensor connected via 30 cm unshielded cable to op-amp with 10 MHz bandwidth and no input RF filtering. At 900 MHz (cell phone band), induced CM voltage of 500 mV gets rectified by the op-amp input junction, creating a DC offset of 50 mV (0.5% of full-scale on a 10V sensor). System fails IEC 61000-4-3 Level 2 (3 V/m) with performance criterion B (temporary degradation).

Op-amp RF rectification: All op-amps exhibit EMI rectification -- RF signals at the input get demodulated by the non-linear input stage, creating DC offsets proportional to RF power. This occurs even if the signal is well outside the op-amp bandwidth. Solution: Filter RF BEFORE the op-amp input pins with RC or LC filters.

Frequency gaps in immunity: Many designs are tested only at spot frequencies. In production, RF sources can be at any frequency. Ensure protection is broadband, not tuned to specific test frequencies.

4.3.3 EFT Burst Protection (IEC 61000-4-4) Major

Electrical Fast Transients (EFT) simulate the interference caused by switching of inductive loads (relays, contactors, motors) sharing the same power distribution. EFT consists of bursts of fast pulses (5 ns rise time, 50 ns duration) at repetition rates up to 100 kHz.

IEC 61000-4-4 Test Levels

LevelPower Port (kV)Signal/Control Port (kV)Rep Rate (kHz)
10.50.255
21.00.55
32.01.05
44.02.02.5

EFT Pulse Characteristics

Single pulse: 5 ns rise time, 50 ns pulse width (at 50% amplitude)
Burst duration: 15 ms
Burst period: 300 ms
Source impedance: 50 ohm

Spectral content: extends to 1/(pi*tr) = 1/(pi*5ns) = 64 MHz
Energy per pulse at 4 kV: E = V^2 * t / (2*Z) = 4000^2 * 50e-9 / (2*50) = 8 uJ
Average power during burst: 8 uJ * 2500 pulses/burst / 0.3s = 66.7 mW

Coupling mechanism to signal cables:
- Capacitive coupling clamp (33 pF per CISPR 16)
- Coupled voltage to cable: V_coupled = V_eft * C_clamp / (C_clamp + C_cable)
- Typical: V_coupled = 2000V * 33pF / (33pF + 200pF) = 283V peak on signal cable

Protection Design

  1. Identify vulnerable ports: AC/DC power input, signal cables (especially long cables > 1m), control interfaces.
  2. For power ports: the EMI input filter (designed for conducted emissions) typically provides adequate EFT attenuation if it includes series inductance. Verify that filter capacitors can handle the transient voltage.
  3. For signal/control ports: add small capacitors (100 pF - 1 nF) from each signal to ground at the connector. These absorb the fast pulse energy before it propagates into the circuit.
  4. Ensure ground connections at connectors are low impedance: the EFT common-mode current must flow to ground without creating ground bounce that upsets the system.
  5. Use ferrite beads or common-mode chokes on signal cables to increase impedance to fast transients.
  6. Verify software/firmware can tolerate momentary communication errors (EFT typically causes data corruption, not hardware damage).

Industrial sensor interface with EFT protection: RS-485 bus with 50m cable. At PCB entry: common-mode choke (600 ohm at 100 MHz), followed by 2.2 nF ceramic caps from each line to ground, then TVS diode (SMBJ6.0A) for overvoltage clamping. Cable shield connected to chassis at connector shell. Ferrite sleeve over cable bundle at entry point. System passes Level 4 (2 kV on signal port) with Criterion A.

RS-485 with only IC-level protection: RS-485 transceiver with built-in +/- 15 kV ESD protection but no external EFT filtering. IC protection handles single ESD events but not repetitive EFT bursts (2500 pulses per burst). The cumulative charge injection through the protection diodes causes latch-up after 5-10 bursts. System requires power cycle after EFT test -- fails Criterion C (loss of function).

EFT vs. ESD -- different threats: ESD is a single high-energy event; EFT is thousands of smaller events in rapid succession. Protection must handle the repetition rate without accumulating charge or heat. TVS diodes that handle single ESD events may overheat during continuous EFT bursts.

Filter capacitor voltage rating: EFT voltages can be very high (4 kV). Capacitors used for EFT filtering must be rated for the applied voltage -- or be protected by upstream clamping devices. A 16V ceramic cap in a 2 kV EFT environment will fail catastrophically.

4.3.4 Surge Protection (IEC 61000-4-5) Critical

Surge immunity tests simulate lightning-induced transients and large switching transients on power and telecom lines. Unlike ESD and EFT, surge involves high energy (joules, not microjoules) and requires robust protection components capable of absorbing or diverting substantial energy without damage.

IEC 61000-4-5 Test Levels

LevelLine-to-Line (kV)Line-to-Earth (kV)Waveform
10.50.51.2/50 us (voltage), 8/20 us (current)
21.01.01.2/50 us, 8/20 us
32.02.01.2/50 us, 8/20 us
44.04.01.2/50 us, 8/20 us
Special (Telecom)6.06.010/700 us (telecom)

Surge Energy Calculation

Combination wave generator (1.2/50 us open circuit, 8/20 us short circuit):
- Source impedance: 2 ohm (line-to-line), 12 ohm (line-to-earth)
- Peak current at 4 kV, 2 ohm: I_peak = 4000/2 = 2000 A
- Energy in 8/20 us pulse at 2 kV, 2 ohm:
E = integral(V*I*dt) approx = V_clamp * I_peak * t_eff
For MOV clamping at 600V: E = 600 * (2000/2) * 20e-6 = 12 J (!)

For line-to-earth (12 ohm source):
- Peak current at 4 kV: I_peak = 4000/12 = 333 A
- Energy: E = 600 * 333 * 20e-6 = 4 J

This is MUCH more energy than ESD (4.8 mJ) or EFT (8 uJ per pulse).
Protection components must handle joules of energy!

Protection Component Selection

Surge protection hierarchy (outside-in):

1. Primary protection (at entry point):
   - Gas Discharge Tube (GDT): Handles 10+ kA, slow response (us)
     Example: Bourns 2035-09-SM (90V sparkover, 10 kA 8/20 us)
   - Metal Oxide Varistor (MOV): Handles 3-10 kA, medium speed
     Example: Littelfuse V14E250P (250 Vrms, 6.5 kA 8/20 us, 55J)

2. Secondary protection (after primary):
   - TVS diode: Fast response (< 1 ns), moderate current (50-400A)
     Example: Littelfuse SMBJ170A (170V standoff, 200A peak)
   - Thyristor surge protector: Crowbar-type, high current
     Example: Bourns TISP4240M3BJ (240V, 100A 8/20 us)

3. Tertiary protection (at IC):
   - Low-capacitance TVS or IC built-in protection
   - Handles residual let-through from upstream stages

Coordination: Each stage must limit voltage to within the rating of
the next downstream stage. Allow 2:1 voltage ratio between stages.
            

AC power input with coordinated surge protection (Level 4, 4 kV): Stage 1: MOV (275 Vrms, 10 kA) across L-N, L-PE, N-PE at the AC input. Limits voltage to 700V peak. Stage 2: After EMI filter inductor (which provides ~10 us delay), TVS (SMBJ400A) clamps to 560V. Stage 3: After bridge rectifier, TVS (SMBJ200A) on DC bus clamps to 270V. Each stage has series impedance (inductor/resistor) between it and the next stage to allow coordination. System survives 5 positive + 5 negative surges at 4 kV L-N and L-PE without damage (Criterion B).

Single MOV with no coordination: Only one MOV (275 Vrms) at AC input. No downstream protection. MOV lets through 700V peak, which exceeds the 450V rating of the DC bus electrolytic capacitors and the 600V rating of the bridge rectifier. First 4 kV surge destroys the bridge rectifier. MOV itself survives but passes enough energy to damage downstream components.

MOV degradation: MOVs degrade with each surge event -- clamping voltage drops slightly, leakage current increases. After many surge events, the MOV can draw significant leakage current and overheat. Include thermal disconnect (built into many MOV packages) and plan for replacement in field-maintainable equipment.

Coordination timing: GDTs have 0.5-3 us response time. During this delay, the downstream TVS must handle the full surge current alone. Size the TVS for the initial surge current before the GDT fires.

4.3.5 Conducted RF Immunity (IEC 61000-4-6) Major

Conducted RF immunity tests simulate the effect of RF transmitters coupling onto cables connected to equipment. The test injects 150 kHz to 80 MHz RF onto all cables (power, signal, control) to verify equipment operates correctly. This test complements IEC 61000-4-3 (radiated immunity) for frequencies below 80 MHz where radiated testing is impractical.

IEC 61000-4-6 Test Levels

LevelVoltage (V emf)Voltage (dBuV)Application
11120Protected environment
23130Residential, commercial
310140Industrial
430150Heavy industrial

Test Setup and Coupling Methods

Injection methods:
1. CDN (Coupling/Decoupling Network): Direct injection into cable
- Source impedance: 150 ohm (through 6 dB pad from 50 ohm source)
- Common-mode injection on all conductors simultaneously

2. EM-Clamp: Inductive/capacitive coupling via clamp around cable
- Used when CDN is not practical (e.g., fiber, coax, large cable bundles)

3. BCI (Bulk Current Injection) probe: Current transformer around cable
- Alternative method, measures injected current rather than voltage

Modulation: 1 kHz AM, 80% depth (simulates voice-modulated transmitter)
Sweep: 150 kHz to 80 MHz, 1% frequency steps, 3s dwell per frequency

Protection Strategies

  1. Add common-mode filtering at every cable port: ferrite beads (600+ ohm at 30 MHz) or common-mode chokes provide high impedance to injected RF.
  2. Add bypass capacitors (1-10 nF) from each cable signal line to ground at the connector. These create a low-pass filter with the cable inductance.
  3. Use shielded cables with shield grounded at the equipment enclosure. Shield provides a return path for CM current before it enters the PCB.
  4. Ensure all power supply decoupling is effective at the test frequencies (150 kHz - 80 MHz). 100 nF ceramics provide good bypass in this range.
  5. Test for AM demodulation: The 1 kHz AM modulation can be detected by non-linear junctions (transistor inputs, diode detectors) and appear as 1 kHz audio noise or DC offset.
  6. Pay special attention to audio circuits, sensor inputs, and ADC reference lines -- these are most susceptible to conducted RF.

Industrial I/O module with conducted RF immunity: Each analog input channel: ferrite bead (Murata BLM18PG601SN1, 600 ohm at 100 MHz) in series, followed by 4.7 nF C0G capacitor to ground, then 100 ohm series resistor before ADC pin. Provides 40 dB of RF attenuation at 10 MHz, 60 dB at 80 MHz. All digital I/O have common-mode chokes at connector. Passes Level 3 (10V) with Criterion A on all ports.

Audio amplifier input with no RF filtering: Audio input connected via RCA jack, 50 cm cable to first gain stage (op-amp with 60 dB gain). No RF filter at input. At 30 MHz, 3V conducted RF with 80% AM modulation is demodulated by the op-amp input junction, producing 1 kHz audio tone at 50 mV output level. This is audible (1% of full scale) and fails Level 2 with Criterion B.

4.3.6 Power Frequency Magnetic Field (IEC 61000-4-8) Minor

Equipment installed near power cables, transformers, or motor drives can be exposed to intense 50/60 Hz magnetic fields. IEC 61000-4-8 defines immunity test levels for these power-frequency fields. This is primarily a concern for equipment with magnetic-field-sensitive components (CRTs, magnetic sensors, transformers, inductors).

IEC 61000-4-8 Test Levels

LevelContinuous (A/m)Short Duration (A/m)Application
11--Protected environment
23--Residential, commercial
310--Industrial
430300Near power substations
51001000Power plant environment

Magnetic Field Effects

Induced voltage in a loop (Faraday's law):
V = -N * dPhi/dt = -N * A * dB/dt = N * A * B_peak * 2*pi*f

Where: N = number of turns, A = loop area (m^2), B = mu_0 * H

Example: 30 A/m field at 50 Hz, PCB loop area 10 cm^2:
B = 4*pi*10^-7 * 30 = 37.7 uT
V = 1 * 10e-4 * 37.7e-6 * 2*pi*50 = 1.18 uV

This is small for digital circuits but significant for:
- High-gain amplifiers (60+ dB gain, uV input signals)
- Precision ADCs (24-bit, LSB = few uV)
- Current sense shunts (mV full-scale)
- Hall sensors and magnetometers

For transformer/inductor cores:
External B field adds to operating flux, potentially causing saturation
30 A/m = 37.7 uT -- significant if core operates near saturation

Mitigation Techniques

  1. Minimize sensitive loop areas: route differential pairs tightly, use ground planes directly adjacent to sensitive traces.
  2. Orient PCB perpendicular to expected magnetic field direction (minimize flux linkage).
  3. Use magnetic shielding (mu-metal) around sensitive components if required (Hall sensors, fluxgate magnetometers).
  4. For inductors/transformers: ensure adequate saturation margin considering external field contribution.
  5. Use differential sensing where possible: common-mode magnetic field couples equally to both conductors and cancels in the differential measurement.
  6. Design software filtering to reject 50/60 Hz: use notch filters or integrate over full power-line cycles in ADC measurements.

Precision current sensor near power bus: Shunt resistor (1 mohm) measuring 100A DC bus current. Signal level: 100 mV full scale. Kelvin-connected sense traces routed as tight differential pair (0.15 mm spacing) with ground plane directly above. Loop area: 2 mm x 10 mm = 20 mm^2. At 30 A/m: induced voltage = 0.12 uV -- negligible vs. 100 mV full scale. Instrumentation amplifier with CMRR > 100 dB at 50 Hz rejects any remaining common-mode pickup.

Precision ADC with large sense loop: 24-bit ADC measuring millivolt-level thermocouple signal. Sense traces routed 5 cm apart on different layers (loop area: 50 mm x 5 mm = 250 mm^2). At 30 A/m, 50 Hz: induced voltage = 1.48 uV. With 100x gain and 24-bit resolution on 2.5V reference: LSB = 149 nV. The 1.48 uV pickup = 10 LSB of noise at 50 Hz. Fails to meet specified accuracy in 30 A/m field.