Tutorial 5.6: High-Speed Signal Layout
Routing techniques for DDR4, USB3, PCIe, Ethernet, and HDMI with impedance control and timing closure
Routing techniques for DDR4, USB3, PCIe, Ethernet, and HDMI with impedance control and timing closure
High-speed signal routing requires disciplined attention to impedance continuity, return path integrity, timing alignment, and crosstalk management. Every rule has a physical basis in electromagnetic field behavior. This tutorial provides specific, actionable routing guidelines for the most common high-speed interfaces encountered in modern PCB designs.
A signal requires high-speed layout techniques when the trace length exceeds 1/6 of the signal's wavelength (one-way flight time exceeds 1/6 of the rise time):
Critical Length = Rise_Time * c / (6 * sqrt(Dk))
Example: Signal with 500ps rise time on FR-4 (Dk=4.0):
L_critical = 500e-12 * 3e8 / (6 * 2.0) = 12.5mm
If trace length > 12.5mm, transmission line effects are significant.
Common interfaces and their critical lengths (FR-4):
SPI at 10 MHz (tr=5ns): 125mm (most traces are fine)
RGMII at 125 MHz (tr=1ns): 25mm (moderate concern)
DDR4 at 1200 MHz (tr=200ps): 5mm (ALL traces are critical)
USB 3.2 (tr=100ps): 2.5mm (extremely critical)
PCIe Gen4 (tr=35ps): 0.9mm (every mm matters)
For SerDes interfaces (USB3, PCIe, SATA), the total channel loss budget is shared between:
| Loss Component | Typical Allocation | How to Minimize |
|---|---|---|
| PCB trace (conductor + dielectric) | 40-60% of budget | Use low-loss material, shorter traces, wider traces |
| Via transitions | 5-15% of budget | Minimize transitions, use blind vias, back-drill |
| Connectors | 10-20% of budget | Use high-frequency rated connectors |
| AC coupling capacitors | 5-10% of budget | Use small package (0201/0402), minimize stub |
| Package (BGA to die) | 10-20% of budget | Fixed by IC vendor - cannot control |
All impedance-controlled nets route on their designated layers with the correct trace width. No impedance-controlled trace routes on a non-controlled layer. Transitions between layers maintain impedance through proper via design.
| Interface | Preferred Layer | Reason | Reference Plane |
|---|---|---|---|
| DDR4 Data (DQ, DQS) | Outer layers (L1, L8) | Shortest path, best impedance control | Adjacent GND plane |
| DDR4 Address/CMD | Inner signal layers | Longer traces acceptable, less critical timing | Adjacent GND/PWR plane |
| USB 3.x TX/RX | Outer layers preferred | Minimum loss, best impedance | Adjacent GND plane |
| PCIe TX/RX | Inner stripline | Better shielding, less radiation | Dual GND reference (both sides) |
| HDMI/DisplayPort | Inner stripline | EMC compliance (FCC/CE) | Dual GND reference |
| Ethernet (SGMII) | Any controlled layer | 100 ohm differential, transformer coupled | Adjacent GND plane |
| LVDS | Any controlled layer | 100 ohm differential, noise immune | Adjacent GND plane |
The reference (return) plane beneath every high-speed signal trace is continuous and unbroken. No splits, slots, via clusters, or routing channels interrupt the return current path. Any necessary plane openings have been evaluated for their impact.
When a signal trace crosses a plane gap:
Signal trace: ==========================================
Plane (GND): ======== GAP ============
^ ^
Return current CANNOT cross here
Must detour around the gap
Effects:
1. Impedance spike at the gap (can exceed +50% Z change)
2. Return current takes long path around gap (increased loop area)
3. Loop area increase = antenna (EMI radiation at signal frequency)
4. Crosstalk increase with any other signal near the gap
5. Timing skew if asymmetric gap affects diff pair differently
Rule: NEVER route a high-speed signal across a reference plane gap.
If unavoidable, provide stitching capacitors (100nF) at the crossing point
to provide AC continuity between the two plane sections.
DDR4 data bus routes on Layer 1 with a solid, unbroken ground plane on Layer 2 underneath the entire routing channel. No other signals route on Layer 2 in this area. Via density under the DDR routing is minimized - only power vias for DDR VTT/VDDQ pass through, with plane restored between vias.
DDR4 data traces on Layer 1 cross over a 3.3V/1.8V plane split on Layer 2. At the split boundary, return current must flow 15mm around the gap. Signal integrity simulation shows 30% impedance spike and 200ps timing skew between DQ bits. Board fails DDR4 write leveling calibration.
| Parameter | Requirement | Notes |
|---|---|---|
| Data impedance (SE) | 40 ohm (+/- 10%) | Some SoCs specify 50 ohm; check datasheet |
| DQS impedance (diff) | 80-100 ohm diff | Match to data impedance x2 |
| Address/CMD impedance | 40 ohm SE | Point-to-point topology |
| Clock impedance | 80-100 ohm diff | Match to address length |
| DQ-to-DQS matching | +/- 2.5mm within byte | Most critical timing constraint |
| Byte-to-byte matching | +/- 5mm (relaxed) | DQ groups can differ from each other |
| ADDR/CMD to CLK | +/- 5mm | All address/cmd relative to clock |
| Crosstalk spacing | >= 3x trace width (3W) | Between byte lanes minimum |
| Max trace length | Vendor-specific (typ 50-75mm) | Check SoC design guide |
| Parameter | Gen 1 (5 Gbps) | Gen 2 (10 Gbps) |
|---|---|---|
| Differential impedance | 85 ohm +/- 15% | 85 ohm +/- 10% |
| Intra-pair skew | < 5 mil | < 2 mil |
| Max PCB trace length | 150mm | 100mm |
| Insertion loss budget (PCB) | -4 dB @ 2.5 GHz | -6 dB @ 5 GHz |
| Coupling spacing to other pairs | >= 4x trace width | >= 5x trace width |
| Via transitions allowed | 2 max (with return vias) | 1 preferred |
| Reference plane breaks | None allowed | None allowed |
| AC coupling cap placement | Near transmitter | Near transmitter (series) |
| Parameter | Gen 3 (8 GT/s) | Gen 4 (16 GT/s) |
|---|---|---|
| Differential impedance | 85 ohm +/- 15% | 85 ohm +/- 10% |
| Intra-pair skew | < 5 mil | < 2 mil |
| Max PCB trace length (connector) | 250mm total | 150mm total |
| Insertion loss (PCB) | -8 dB @ 4 GHz | -8 dB @ 8 GHz |
| Lane-to-lane spacing | >= 5W | >= 5W |
| Preferred layer | Stripline (shielded) | Stripline (required) |
| Material | FR-4 acceptable | Low-loss (Df < 0.010) recommended |
| AC coupling caps | 100nF, 0402, near TX | 100nF, 0201/0402, near TX |
| Parameter | RGMII | SGMII |
|---|---|---|
| Impedance | 50 ohm SE | 100 ohm differential |
| TX group matching | +/- 50ps (5mm) to TX_CLK | Intra-pair +/- 5 mil |
| RX group matching | +/- 50ps (5mm) to RX_CLK | Intra-pair +/- 5 mil |
| Max trace length | 100mm (SoC to PHY) | 150mm |
| Crosstalk spacing | >= 3W | >= 4W |
| Special requirement | 2ns TX_CLK delay (added by PHY or PCB) | AC coupling caps at PHY |
| Parameter | HDMI 2.0 (TMDS) | DisplayPort 1.4 (HBR3) |
|---|---|---|
| Differential impedance | 100 ohm +/- 10% | 100 ohm +/- 10% |
| Intra-pair skew | < 5 mil | < 3 mil |
| Inter-pair length match | +/- 2mm between data lanes to clock | +/- 2mm between lanes |
| Max PCB trace length | 100mm (connector to IC) | 150mm |
| Lane-to-lane spacing | >= 4W (5W preferred) | >= 5W |
| Preferred routing layer | Stripline (EMC compliance) | Stripline (required for EMC) |
| Connector pin assignment | Per HDMI spec (check DDC/CEC routing) | Per DP connector spec |
| ESD protection | Required at connector (low-capacitance TVS) | Required at connector |
| Parameter | MIPI CSI-2 (Camera) | MIPI DSI (Display) |
|---|---|---|
| Differential impedance | 100 ohm +/- 10% | 100 ohm +/- 10% |
| Intra-pair skew | < 5 mil | < 5 mil |
| Max trace length | 100mm (150mm for low data rate) | 100mm |
| Clock-to-data matching | +/- 5mm | +/- 5mm |
| Spacing between lanes | >= 3W | >= 3W |
| Guard ground | Recommended between lanes | Recommended |
| EMC consideration | Short traces preferred (reduces emission) | Keep away from antenna |
RGMII specification requires a 2ns delay on the TX_CLK relative to TX_DATA (and RX_CLK relative to RX_DATA) for proper data sampling. Some PHY chips include internal delays (check datasheet for "Internal Delay" or "Add Delay" register settings). If using internal delays, do NOT add PCB delay (length matching data to clock). If the PHY has no internal delay, you must add ~300mm of trace length to the clock (or use an external delay line). Misunderstanding this requirement is one of the most common causes of Ethernet link failure.
Parallel high-speed traces maintain minimum spacing to limit crosstalk to acceptable levels. The "3W rule" or tighter spacing requirements per interface specification are enforced. No long parallel runs between different signal groups.
| Scenario | Minimum Spacing | Coupled Length Limit |
|---|---|---|
| Same bus, same byte (DDR DQ) | 1.5W (3W preferred) | Full trace length acceptable |
| Different byte lanes | 3W minimum | No limit if spacing met |
| Clock to data | 5W minimum | Minimize parallel run |
| High-speed diff pair to diff pair | 4-5x diff pair width | No limit if spacing met |
| High-speed to general signal | 4W | < 20mm parallel recommended |
| Sensitive analog to digital | 5W or 0.5mm min | Minimize any parallel run |
In the BGA breakout region, traces from different interfaces often run parallel at minimum spacing for 5-10mm. A DDR data bit routed adjacent to a PCIe TX pair in the breakout zone can inject switching noise. Solution: Plan BGA pin assignment to keep different interfaces in separate quadrants. Route interface groups through dedicated escape corridors with spacing between groups.
Every high-speed signal via that transitions between layers has an adjacent ground return via placed within 0.5mm. Return vias connect the reference planes of both layers. For differential pairs, return vias are placed symmetrically between or adjacent to the pair.
Single-Ended Signal Via Transition:
Layer 1 (ref: L2 GND) ----[Signal Via]---- Layer 6 (ref: L5 GND)
[Return Via]
connects L2 GND to L5 GND
Return via distance: <= 0.5mm (20mil) from signal via
Best: immediately adjacent (touching anti-pads)
Differential Pair Via Transition:
[Via P] [Return Via] [Via N]
or
[Return Via] [Via P] [Via N] [Return Via]
For diff pairs: place return via(s) symmetrically
One return via minimum; two return vias (flanking) for > 5 Gbps
Without a return via, the return current must find an alternate path between the two reference planes. This creates a large loop area that:
High-speed nets have no unterminated stubs. T-junctions are eliminated by daisy-chain topology. Via stubs are controlled by blind vias, via-in-pad, or back-drilling. Test point connections use zero-length stubs.
| Stub Source | Typical Length | Problem Frequency | Solution |
|---|---|---|---|
| Through-hole via stub | 0.5-1.5mm | 25-75 GHz (quarter-wave) | Back-drill, blind via, or via-in-pad |
| T-junction to unused pin | 2-10mm | 4-19 GHz | Daisy-chain topology, end termination |
| Test point branch | 1-5mm | 7-37 GHz | Place test point IN-LINE, not as branch |
| Unused connector pin trace | 5-20mm | 2-7 GHz | Remove trace to unused pin, terminate if needed |
| Series component (0 ohm) body | 0.5-1mm | 37-75 GHz (usually OK) | Use 0201/0402, minimize pad size |
Maximum acceptable stub length (causes 10% impedance variation):
L_max = Rise_Time * v_prop / 4
Where v_prop = c / sqrt(Dk) = 1.5e8 m/s for FR-4
Interface stub budgets:
DDR4 (200ps rise): L_max = 200e-12 * 1.5e8 / 4 = 7.5mm (via stubs usually OK)
USB 3.2 Gen1 (100ps): L_max = 3.75mm (marginal for through vias)
PCIe Gen3 (50ps): L_max = 1.9mm (back-drill if stub > 1mm)
PCIe Gen4 (35ps): L_max = 1.3mm (back-drill required for most stackups)
56G PAM4 (20ps): L_max = 0.75mm (HDI/blind vias essential)
PCIe Gen4 lanes route on Layer 3 (stripline). Signal vias are blind vias from L1 to L3, creating zero stub length. No T-junctions exist - all connections are point-to-point. Test points are placed in-line with zero-length branches using via-in-pad test pads.
PCIe Gen4 lanes use through-hole vias on a 1.6mm board with signal on Layer 3. Via stub from L3 to L8 = 1.0mm. No back-drill specified. Additionally, a debug header creates 8mm T-junction stubs on each lane. Eye diagram shows 40% eye closure due to reflections.
Design > Net Classes - create classes for each interface (DDR4_DQ, DDR4_ADDR, USB3_TX, PCIe_Lane0, etc.)Layer Stack Manager > Impedance - define profiles linking to stackup geometryDesign > Differential Pairs - define P/N pairing (auto-detect from naming convention: _P/_N, +/-)Design Rules > High Speed > Matched Net Lengths - set groups and tolerancesInteractive Differential Pair Routing mode. Enable "Timing Vision" overlay for real-time length displayTools > Interactive Length Tuning (accordion or trombone style)Board Setup > Net Classes - define track width, clearance, via sizes per classRoute > Route Differential Pair (D key during routing)Route > Tune Track Length for single-ended, Route > Tune Diff Pair Length for pairsBoard Setup > Custom Rules for advanced constraints (DRC expressions)Inspect > Net Inspector shows trace lengths per netSetup > ConstraintsConstraint Manager > Electrical > Topology - define daisy-chain vs star, T-junction limitsRoute > Delay Tune with configurable amplitude, spacing, and styleAnalyze > Signal Integrity (Allegro SI) for IBIS simulation directly from layoutRoute > Bus Router for parallel high-speed buses with auto-spacingRun SI simulation (IBIS or S-parameter) when any of these conditions exist:
Length matching reports typically show trace length only, not including via transition delay. A via through a 1.6mm board adds approximately 8-10ps of delay (equivalent to ~1.5mm of trace length in FR-4). For interfaces with tight timing budgets (DDR4 DQ-to-DQS), this via delay difference can consume a significant portion of the matching tolerance. If one byte lane has 2 layer transitions while another has 0, the via delay difference is ~20ps (3mm equivalent). Account for this by either: (1) ensuring all nets in a group have the same number of via transitions, or (2) subtracting via delay from the trace length budget.