Tutorial 5.7: Silkscreen & Solder Mask
Design rules for silkscreen readability, solder mask clearance, and assembly marking per IPC standards
Design rules for silkscreen readability, solder mask clearance, and assembly marking per IPC standards
Silkscreen and solder mask are often treated as afterthoughts, but they directly impact assembly quality, field serviceability, and manufacturing yield. Proper silkscreen marking prevents assembly errors (wrong orientation of polarized components). Proper solder mask design prevents solder bridges and ensures reliable joints.
Studies show that assembly defects related to incorrect component orientation account for 5-8% of all placement errors in production. Clear, unambiguous silkscreen markings can reduce this to less than 1%. Similarly, proper solder mask design reduces bridging defects on fine-pitch components by up to 70% compared to designs with inadequate mask dams.
| Design Aspect | Manufacturing Impact | Field Impact |
|---|---|---|
| Clear ref-des labeling | Faster visual inspection, easier rework targeting | Faster troubleshooting, correct replacement |
| Polarity marks | Prevents reversed component placement | Prevents field replacement errors |
| Adequate mask dams | Prevents solder bridging between pads | Fewer field failures from latent shorts |
| Proper mask clearance | Clean solder joints, no contamination | Better long-term reliability |
| Test point labeling | Faster ICT/functional test setup | Faster field diagnosis |
Every component has a visible reference designator that does not overlap pads, other silk, or extend beyond board edges. Minimum text height 0.8mm, minimum stroke width 0.15mm. Text orientation is consistent (readable from one or two directions).
| Parameter | Minimum | Recommended | Large/Clear |
|---|---|---|---|
| Text height | 0.8mm (32mil) | 1.0mm (40mil) | 1.27mm (50mil) |
| Stroke width | 0.15mm (6mil) | 0.18mm (7mil) | 0.2mm (8mil) |
| Height:Stroke ratio | 5:1 minimum | 6:1 typical | 6:1 to 8:1 |
| Character spacing | 0.1mm | 0.15mm | 0.2mm |
| Silk-to-pad clearance | 0.1mm | 0.15mm | 0.2mm |
Use Tools > Autoposition Component Text to automatically position ref-des labels. Configure in Design Rules > Silkscreen > Silk to Pad Clearance (set to 0.15mm). Use Design Rules > Silkscreen > Silk Over Component Pads to catch violations. Run DRC and fix manually with Edit > Align > Position Component Text.
Use Edit > Set Text Sizes to globally change all reference designator sizes. KiCad DRC checks for silk-over-pad violations automatically. Use Inspect > List Inspection to find components with hidden or off-board reference designators. Bulk edit text properties through the Properties panel with multi-select.
Use Display > Status > Text Status to list all text items. Run Tools > Quick Reports > Silkscreen for coverage report. Use Edit > Text > Auto-Arrange for automatic positioning. Check DRC for silk violations in Manufacture > Assembly category.
All ref-des at 1.0mm height, 0.18mm stroke. Every IC shows pin 1 dot. All polarized components show polarity mark. Text reads from bottom or right consistently. No text overlaps pads. Even 0402 passives have ref-des visible (placed between components).
Half the ref-des are at 0.5mm height (unreadable after manufacturing). Multiple labels overlap IC pads. Some text extends beyond board edge (will not print). Text orientation is random (6 different angles). No polarity marks on capacitors. Assembly technician cannot identify components for rework.
Every polarized component has a clear orientation indicator in the silkscreen: cathode band on diodes, positive/negative mark on electrolytic capacitors, dot/triangle on ICs for pin 1, anode mark on LEDs.
| Component Type | Standard Mark | IPC-7351 Convention |
|---|---|---|
| Diode (all types) | Cathode band (line at cathode end) | Line on cathode side of outline |
| LED | Cathode indicator or "+" near anode | Cathode mark on footprint |
| Electrolytic capacitor | "+" near positive terminal | "+" mark in courtyard |
| Tantalum capacitor | Band or "+" at anode (positive) | Band at positive end |
| IC/BGA (Pin 1) | Dot at pin 1 corner | Dot or chamfer at pin 1 |
| Connector (Pin 1) | Arrow or "1" at pin 1 | Pin 1 indicator mark |
| Transistor/MOSFET | Outline showing pin arrangement | Matches component outline drawing |
Tantalum capacitors mark the POSITIVE (anode) terminal with a band, which is the opposite of electrolytic capacitors that mark the NEGATIVE terminal with a stripe. A designer unfamiliar with tantalum marking may reverse the polarity in the footprint. Always verify the footprint orientation against the manufacturer's datasheet land pattern drawing. Additionally, some Asian-manufactured electrolytics mark the NEGATIVE terminal differently than Western convention.
Every diode has a cathode band in silkscreen matching the component body marking. All electrolytic and tantalum capacitors show their polarity. Every IC has a clear pin 1 dot visible outside the component body outline. LEDs show cathode mark with a flat edge on the circle outline. Verification pass confirms zero missing polarity marks.
Half the diodes have no cathode band (just a rectangle outline). Tantalum caps show a "+" on the wrong end (designer confused anode band with cathode mark). Three BGAs have no pin 1 indicator at all. Two connectors have no pin 1 arrow. Assembly house places 5% of components reversed, causing field failures.
| Package | What to Verify | Common Error |
|---|---|---|
| SOD-323 / SOD-123 (Diode) | Cathode band on correct end | Band placed on anode side |
| SOT-23 (Transistor/MOSFET) | Pin numbering matches datasheet | Pin 1/3 swapped (varies by manufacturer) |
| QFN (multi-source) | Pin 1 dot position consistent | Different vendors put pin 1 in different corners |
| Electrolytic Cap (SMD) | "+" or "-" mark on correct pad | Marking convention varies by region |
| LED (0603/0805) | Cathode indicator (usually flat/line) | Different LED vendors use different marks |
Every IC package has a clear pin 1 indicator that remains visible after assembly. For BGAs, the pin A1 corner is marked. Assembly drawing shows pin 1 orientation for all ICs. Pin 1 mark is on the copper/mask layer (survives silkscreen wear).
BGA pin A1 corner must be clearly identifiable because:
Best practice: Place THREE indicators for BGA pin A1: (1) Silkscreen dot outside the body outline, (2) Copper/mask feature visible after placement, (3) Assembly layer notation with pin assignment direction.
All designated test points have silkscreen labels indicating their net name or signal function. Test point labels are readable and adjacent to (not overlapping) the test pad. Critical voltage rails and signal names are clearly marked.
Essential test points for power supply debugging:
| Test Point | Location | Purpose |
|---|---|---|
| VIN (input voltage) | After input connector/fuse | Verify input power presence |
| Each regulator output | Regulator output cap | Verify regulation |
| Critical load point | At IC power pin | Check for voltage drop |
| GND (multiple) | Distributed across board | Oscilloscope ground reference |
| Switching node | Regulator SW pin | Debug switching waveform |
| Test Point Type | Pad Diameter | Application | Access Side |
|---|---|---|---|
| ICT test point | 1.0mm (40mil) | Bed-of-nails fixture testing | Bottom (preferred) |
| Manual probe point | 1.5-2.0mm | Lab debugging with scope probes | Top (accessible) |
| Flying probe point | 0.8mm minimum | Bare-board or assembled board test | Either side |
| Header/loop point | Through-hole, 2.54mm pitch | Current measurement, logic analyzer | Top |
Every power rail has a labeled test point with clear voltage indication ("+3V3", "+1V8", "GND"). Communication interfaces have test points at strategic locations (UART_TX, UART_RX near processor). GND test points distributed every 30mm for convenient oscilloscope grounding. Labels at consistent 0.8mm height, all readable from one direction.
Test points exist but have no labels - engineer must trace nets in the design tool to identify them. Several test points are under a shield can (inaccessible). No ground test point within 50mm of the debug header. Power rail test points placed on bottom side under a heatsink.
Solder mask openings (relief) around pads provide adequate clearance without exposing adjacent copper. Mask swell values are set appropriately per pad size and fabricator capabilities. No unintended copper exposure.
| Pad Type | Minimum Mask Clearance | Recommended | Notes |
|---|---|---|---|
| Standard SMD pad | 2 mil (0.05mm) per side | 3 mil (0.075mm) per side | Total opening = pad + 2x clearance |
| Fine-pitch (<0.5mm pitch) | 1.5 mil (0.038mm) | 2 mil (0.05mm) | May require solder mask defined (SMD) |
| BGA pad | 2-3 mil | 3 mil | Or use solder mask defined pad |
| Through-hole pad | 4 mil (0.1mm) | 5 mil (0.125mm) | Larger to accommodate drill tolerance |
| NSMD vs SMD (BGA) | See below | NSMD preferred for reliability | Industry standard for BGAs |
NSMD (Non-Solder Mask Defined) - Preferred for most BGAs:
Mask opening LARGER than copper pad
Copper pad defines the solder joint size
Better fatigue life (solder wraps around pad edge)
Tighter pad-to-pad pitch possible
[===Mask===] [===Mask===]
[pad] gap [pad]
[===Mask===] [===Mask===]
SMD (Solder Mask Defined) - Used when copper spacing is tight:
Mask opening SMALLER than copper pad
Mask opening defines the solder joint size
Allows tighter copper spacing (mask provides clearance)
Used for 0.4mm pitch BGA and below
[Mask][pad overlap][Mask][pad overlap][Mask]
[==pad==] [==pad==]
| Parameter | JLCPCB | PCBWay | Advanced Circuits |
|---|---|---|---|
| Min mask clearance | 2.5 mil (0.065mm) | 2 mil (0.05mm) | 2 mil (0.05mm) |
| Min mask web (between pads) | 3 mil (0.075mm) | 3 mil (0.075mm) | 2.5 mil (0.065mm) |
| Mask registration tolerance | +/- 2 mil | +/- 1.5 mil | +/- 1 mil |
| Min mask dam (LPI) | 3 mil | 3 mil | 3 mil |
A 3-mil mask clearance on a pad expands the mask opening by 3 mil on each side. If a trace runs 5 mil from the pad edge, the mask opening will extend to within 2 mil of the trace, potentially exposing it. This creates a risk of solder bridging to the trace during assembly. Solution: Verify mask-to-trace clearance after applying mask swell. Increase trace-to-pad spacing or reduce mask clearance in tight areas.
Solder mask dams (webs) exist between all fine-pitch component pads to prevent solder bridging. Minimum mask web width meets fabricator capability (typically 3 mil minimum). Where mask dams are not achievable, consider gang-relieving with appropriate pad design.
Mask dam width between two adjacent pads:
Dam = Pitch - Pad_Width - 2 * Mask_Clearance
Example: 0.5mm pitch QFP, 0.3mm pad width, 0.05mm mask clearance
Dam = 0.5 - 0.3 - 2*0.05 = 0.1mm (4 mil) -- OK for most fabs
Example: 0.4mm pitch QFP, 0.25mm pad width, 0.05mm mask clearance
Dam = 0.4 - 0.25 - 2*0.05 = 0.05mm (2 mil) -- TOO THIN for most fabs!
Solutions when dam is too thin:
1. Reduce mask clearance to 1-2 mil (verify with fab)
2. Use SMD (solder-mask-defined) pads
3. Gang-relieve the pads (one mask opening for all pads)
4. Use a different component package with larger pitch
When individual mask dams are not achievable, a single mask opening exposes all pads of one side of a fine-pitch component. This requires:
No silkscreen ink is printed on any exposed copper pad or in any solder mask opening. Silkscreen outlines and text maintain minimum clearance from all pad openings. Fabricators will clip silk over pads, but relying on this creates unreliable markings.
| Scenario | Min Clearance (silk to mask opening) | Recommended |
|---|---|---|
| Silk outline to SMD pad | 0.1mm (4mil) | 0.15mm (6mil) |
| Silk text to SMD pad | 0.1mm (4mil) | 0.2mm (8mil) |
| Silk to through-hole pad | 0.15mm (6mil) | 0.25mm (10mil) |
| Silk to via tent opening | 0.05mm (2mil) | 0.1mm (4mil) |
Altium: Design Rules > Manufacturing > Silk to Solder Mask Clearance - set to 0.1mm minimum. Run DRC to find all violations.
KiCad: DRC automatically checks silk-to-pad overlap. Violations appear as "Silkscreen clipped by solder mask" warnings. Set minimum clearance in Board Setup > Design Rules.
Allegro: Check in Manufacture > Silkscreen DRC category. Set clearance in Constraint Manager manufacturing section.
| Mark Type | Purpose | Placement | Size |
|---|---|---|---|
| Board name/part number | Identification | Visible area on top side | 1.5-2.0mm height |
| Revision code | Version tracking | Near board name | 1.0-1.5mm height |
| Date code placeholder | Manufacturing date tracking | Open area, visible after assembly | 1.0mm height |
| UL/safety marks | Regulatory compliance | Per certification requirements | Per standard (typically 3mm min) |
| Board orientation arrow | Assembly direction reference | Corner near fiducial | 3-5mm arrow |
| Serial number placeholder | Traceability | Barcode-friendly area | Per barcode format |
| Country of origin | Trade compliance | Visible after assembly | 1.0mm height minimum |
| ESD warning symbol | Handling instruction | Near board edge | 5-10mm |
The solder paste (stencil) layer is often overlooked during review but directly impacts assembly yield:
| Pad Type | Paste Ratio (% of pad) | Reasoning |
|---|---|---|
| Standard SMD (0603+) | 100% (same as pad) | Standard paste volume adequate |
| Fine-pitch QFP (<0.5mm) | 80-90% | Reduce paste to prevent bridging |
| BGA pads (0.5mm+ pitch) | 100% | Full paste for reliable joints |
| BGA pads (0.4mm pitch) | 80-90% | Reduced to prevent bridging |
| QFN thermal pad | 50-70% (window pane) | Prevent voiding and tombstoning |
| Large pads (connectors) | Multiple smaller openings | Prevent paste slump and excess solder |
| Through-hole reflow pads | Custom (pin-in-paste design) | Extra paste to fill hole during reflow |
For QFN/DFN exposed pads, use a "window pane" paste pattern:
Full Pad Area: Paste Pattern (60% coverage):
+---------------+ +---+ +---+ +---+
| | | | | | | |
| | +---+ +---+ +---+
| 3.2 x 3.2 | --> +---+ +---+ +---+
| mm | | | | | | |
| | +---+ +---+ +---+
+---------------+ +---+ +---+ +---+
| | | | | |
+---+ +---+ +---+
9 apertures (3x3 grid), each ~0.9x0.9mm
Gaps between: 0.3mm (allows outgassing)
Total paste area: ~60% of pad area
Prevents: Voiding, tombstoning, solder spatter
| Parameter | JLCPCB | PCBWay | Advanced Circuits |
|---|---|---|---|
| Min text height | 1.0mm | 0.8mm | 0.8mm |
| Min stroke width | 0.15mm | 0.15mm | 0.127mm |
| Silk color options | White, Black | White, Black, Yellow, Red | White, Black, Yellow |
| Silk-to-pad clearance | Auto-clipped | Auto-clipped | Must be specified |
| Minimum line width | 0.15mm | 0.1mm | 0.1mm |
| Registration accuracy | +/- 0.15mm | +/- 0.1mm | +/- 0.1mm |
Most fabricators automatically clip (remove) any silkscreen that overlaps solder mask openings. This happens silently - you will not receive a notification. If critical information (like a polarity mark or pin 1 indicator) overlaps a pad, it will be removed without your knowledge. The assembled board will then have no polarity indication for that component. Prevention: Always run the silk-to-mask DRC check and fix all violations BEFORE submitting for fabrication. Never rely on fabricator clipping to "handle" overlapping silk.