Capstone Project 2: Processor PDN Design
Design the power delivery network for a 50A processor operating at 1.0V with a maximum 3% ripple specification. Select capacitors, check for anti-resonance, and verify IR drop.
Project Brief
Objective
Design a PDN that maintains supply voltage within 3% of nominal (1.0V) under all transient load conditions for a 50A processor. The PDN impedance must remain below the target impedance from DC to 500 MHz.
| Parameter | Value | Unit |
|---|---|---|
| Nominal Voltage (Vdd) | 1.0 | V |
| Max Current (Imax) | 50 | A |
| Max Ripple | 3% | (30 mV) |
| Transient di/dt | 50 | A/ns |
| PDN Bandwidth | DC to 500 | MHz |
| Max IR Drop | 10 | mV |
| VRM Location | 15mm from BGA | -- |
Step 1: Target Impedance Calculation
Calculate the target impedance based on voltage tolerance and maximum transient current.
Step 2: Capacitor Selection
Choose bulk, MLCC, and high-frequency capacitors to create a flat PDN impedance profile.
Bulk Capacitors (VRM Output, 10kHz - 1MHz)
MLCC Capacitors (Mid-Range, 1MHz - 100MHz)
High-Frequency Capacitors (100MHz - 500MHz)
Step 3: Anti-Resonance Check
Verify that no anti-resonance peaks exceed the target impedance.
Step 4: IR Drop Check
Verify that DC resistance from VRM to processor does not cause excessive voltage drop.