Engineering Tools & Calculators
Real-time calculators for signal integrity, power integrity, and EMI/EMC analysis. All calculations run locally in your browser.
↔ Signal Integrity
Impedance, Reflections, Crosstalk, Eye Diagram, BER, Channel Budget
⚡ Power Integrity
Target Impedance, Decoupling Optimizer, PDN Analysis
🔎 Diagnostics
Interactive Troubleshooting Wizard for SI, PI, and EMI problems
⚡ Microstrip Impedance Calculator SI
Calculate characteristic impedance of a microstrip trace using the IPC-2141 approximation.
Z0 = (87 / √(εr + 1.41)) × ln(5.98 × h / (0.8 × w + t))
where w = trace width, h = dielectric height, εr = dielectric constant, t = copper thickness (all in mils)
where w = trace width, h = dielectric height, εr = dielectric constant, t = copper thickness (all in mils)
Characteristic Impedance:
--
--
Design Tips:
• For single-ended signals, target 50Ω (industry standard for most interfaces).
• Wider traces lower impedance; thinner dielectric lowers impedance.
• Higher Dk lowers impedance. Low-loss laminates (Dk~3.2-3.7) yield higher Z0 for same geometry.
• This formula is valid for w/h ratios between 0.1 and 3.0. For stripline, use a different formula.
• After etching, trace width is typically 0.5-1.0 mil narrower than artwork; account for etch compensation.
• Copper roughness (Rz) increases effective impedance and loss at frequencies above 5 GHz.
• For single-ended signals, target 50Ω (industry standard for most interfaces).
• Wider traces lower impedance; thinner dielectric lowers impedance.
• Higher Dk lowers impedance. Low-loss laminates (Dk~3.2-3.7) yield higher Z0 for same geometry.
• This formula is valid for w/h ratios between 0.1 and 3.0. For stripline, use a different formula.
• After etching, trace width is typically 0.5-1.0 mil narrower than artwork; account for etch compensation.
• Copper roughness (Rz) increases effective impedance and loss at frequencies above 5 GHz.
↔ Reflection Coefficient Calculator SI
Calculate reflection coefficient (Γ), return loss, and VSWR from characteristic and load impedance.
Γ = (ZL − Z0) / (ZL + Z0)
Return Loss (dB) = −20 × log10(|Γ|)
VSWR = (1 + |Γ|) / (1 − |Γ|)
Return Loss (dB) = −20 × log10(|Γ|)
VSWR = (1 + |Γ|) / (1 − |Γ|)
Reflection Coefficient (Γ): --
|Γ|: --
Return Loss: --
VSWR: --
|Γ|: --
Return Loss: --
VSWR: --
Reference Guide:
• |Γ| < 0.05 (RL > 26 dB): Excellent match, suitable for precision RF applications.
• |Γ| < 0.10 (RL > 20 dB): Good match, acceptable for most high-speed digital links.
• |Γ| < 0.18 (RL > 15 dB): Moderate match, typical minimum for PCB via transitions.
• |Γ| > 0.33 (RL < 10 dB): Poor match, will cause significant signal degradation.
• VSWR of 1.5:1 corresponds to ~14 dB return loss and ~4% reflected power.
• For differential signals, use Z_diff and Z_diff_load in the calculations.
• |Γ| < 0.05 (RL > 26 dB): Excellent match, suitable for precision RF applications.
• |Γ| < 0.10 (RL > 20 dB): Good match, acceptable for most high-speed digital links.
• |Γ| < 0.18 (RL > 15 dB): Moderate match, typical minimum for PCB via transitions.
• |Γ| > 0.33 (RL < 10 dB): Poor match, will cause significant signal degradation.
• VSWR of 1.5:1 corresponds to ~14 dB return loss and ~4% reflected power.
• For differential signals, use Z_diff and Z_diff_load in the calculations.
⚡ Target Impedance Calculator PI
Calculate the target impedance for a power distribution network (PDN).
Ztarget = Vdd × Ripple% / Itransient
A lower target impedance requires more decoupling capacitance and lower-ESR components.
A lower target impedance requires more decoupling capacitance and lower-ESR components.
Target Impedance: --
Allowed Voltage Ripple: --
Allowed Voltage Ripple: --
PDN Design Context:
• Modern SoCs typically require target impedance in the 1-10 mΩ range.
• The VRM controls impedance at DC to ~100 kHz; bulk caps cover 100 kHz-1 MHz; MLCCs cover 1-100 MHz; plane capacitance covers 100 MHz+.
• Anti-resonance peaks between capacitor groups can violate target impedance even if individual caps are adequate.
• Transient current estimates should include worst-case switching scenarios (e.g., exit from sleep mode).
• DDR5: Vdd = 1.1V, 5% ripple, 5A transient yields Z_target = 11 mΩ.
• Use the Decoupling Optimizer below to verify your capacitor network meets this target.
• Modern SoCs typically require target impedance in the 1-10 mΩ range.
• The VRM controls impedance at DC to ~100 kHz; bulk caps cover 100 kHz-1 MHz; MLCCs cover 1-100 MHz; plane capacitance covers 100 MHz+.
• Anti-resonance peaks between capacitor groups can violate target impedance even if individual caps are adequate.
• Transient current estimates should include worst-case switching scenarios (e.g., exit from sleep mode).
• DDR5: Vdd = 1.1V, 5% ripple, 5A transient yields Z_target = 11 mΩ.
• Use the Decoupling Optimizer below to verify your capacitor network meets this target.
📈 Crosstalk Estimator SI
Estimate near-end (NEXT) and far-end (FEXT) crosstalk for coupled microstrip traces.
NEXT ≈ (1/4) × (Kb + Kf) × Vin — saturates for coupled length > critical length
FEXT ≈ Kf × (coupled length / rise time) × Vin
Kb, Kf estimated from s/h ratio; 3W rule: space ≥ 3 × w for <70% crosstalk reduction
FEXT ≈ Kf × (coupled length / rise time) × Vin
Kb, Kf estimated from s/h ratio; 3W rule: space ≥ 3 × w for <70% crosstalk reduction
Kb (backward coupling): --
Kf (forward coupling): --
NEXT (mV per V): --
FEXT (mV per V): --
3W Rule Check: --
Kf (forward coupling): --
NEXT (mV per V): --
FEXT (mV per V): --
3W Rule Check: --
Crosstalk Mitigation Strategies:
• 3W Rule: Center-to-center spacing ≥ 3× trace width gives ~70% reduction in crosstalk.
• 5W Rule: For sensitive signals (clocks, resets), use 5W spacing for >90% reduction.
• Guard traces: Grounded guard traces with via stitching every λ/10 provide additional isolation.
• Layer assignment: Route aggressors and victims on different layers with an interleaving ground plane.
• Stripline advantage: Stripline has ~2× less crosstalk than microstrip for the same geometry due to homogeneous dielectric shielding.
• Differential pairs: Tightly coupled differential pairs reject common-mode crosstalk naturally.
• NEXT is usually the larger concern in parallel buses; FEXT dominates in long serial channels.
• 3W Rule: Center-to-center spacing ≥ 3× trace width gives ~70% reduction in crosstalk.
• 5W Rule: For sensitive signals (clocks, resets), use 5W spacing for >90% reduction.
• Guard traces: Grounded guard traces with via stitching every λ/10 provide additional isolation.
• Layer assignment: Route aggressors and victims on different layers with an interleaving ground plane.
• Stripline advantage: Stripline has ~2× less crosstalk than microstrip for the same geometry due to homogeneous dielectric shielding.
• Differential pairs: Tightly coupled differential pairs reject common-mode crosstalk naturally.
• NEXT is usually the larger concern in parallel buses; FEXT dominates in long serial channels.
⚗ Decoupling Capacitor Optimizer PI
Build a capacitor network and visualize combined impedance vs. frequency. Add capacitors with their parasitics.
Zcap(f) = √( (ESR)2 + (2πf × ESL − 1/(2πf × C))2 )
Parallel combination: 1/Ztotal = Σ 1/Zi
Self-resonant frequency: fSRF = 1 / (2π√(C × ESL))
Parallel combination: 1/Ztotal = Σ 1/Zi
Self-resonant frequency: fSRF = 1 / (2π√(C × ESL))
| # | Capacitance | ESR (mΩ) | ESL (nH) | Qty | SRF | |
|---|---|---|---|---|---|---|
| 1 | -- | |||||
| 2 | -- | |||||
| 3 | -- |
Combined impedance plotted above. Hover for values.
👁 Eye Margin Explorer SI
Evaluate eye diagram margins for high-speed serial links.
Voltage Margin = (Eye Height − 2 × Noise) / Eye Height × 100%
Timing Margin = (Eye Width − 2 × Jitter) / Eye Width × 100%
Typical SerDes specs require >30% margin in both dimensions for robust operation.
Timing Margin = (Eye Width − 2 × Jitter) / Eye Width × 100%
Typical SerDes specs require >30% margin in both dimensions for robust operation.
Eye Height After Noise: --
Eye Width After Jitter: --
Voltage Margin: --
Timing Margin: --
Overall Assessment: --
Eye Width After Jitter: --
Voltage Margin: --
Timing Margin: --
Overall Assessment: --
Eye Diagram Interpretation:
• Eye height represents voltage margin: the vertical opening available for the receiver slicer.
• Eye width represents timing margin: the horizontal window for valid data sampling.
• Jitter closes the eye horizontally (deterministic + random components).
• Noise closes the eye vertically (thermal, crosstalk, power supply coupling).
• Modern SerDes use eye masks with minimum height/width specifications.
• Equalization (CTLE + DFE) can recover 10-15 dB of channel loss, dramatically opening the eye.
• PAM4 eyes have 3 smaller openings with ~9.5 dB less margin than NRZ eyes.
• Eye height represents voltage margin: the vertical opening available for the receiver slicer.
• Eye width represents timing margin: the horizontal window for valid data sampling.
• Jitter closes the eye horizontally (deterministic + random components).
• Noise closes the eye vertically (thermal, crosstalk, power supply coupling).
• Modern SerDes use eye masks with minimum height/width specifications.
• Equalization (CTLE + DFE) can recover 10-15 dB of channel loss, dramatically opening the eye.
• PAM4 eyes have 3 smaller openings with ~9.5 dB less margin than NRZ eyes.
📊 BER Estimator SI
Estimate bit-error rate from eye height and noise using Q-factor analysis.
Q = Eye Height / (2 × σnoise)
BER ≈ 0.5 × erfc(Q / √2)
Q ≥ 7 corresponds to BER ≤ 10−12. Most SerDes links target Q > 6 (BER < 10−9).
BER ≈ 0.5 × erfc(Q / √2)
Q ≥ 7 corresponds to BER ≤ 10−12. Most SerDes links target Q > 6 (BER < 10−9).
Q Factor: --
Estimated BER: --
Assessment: --
Estimated BER: --
Assessment: --
Q-Factor Reference Table:
• Q = 3.09 → BER = 10-3 (minimum for FEC to function)
• Q = 3.72 → BER = 10-4
• Q = 4.75 → BER = 10-6
• Q = 5.99 → BER = 10-9 (typical raw BER target without FEC)
• Q = 7.03 → BER = 10-12 (gold standard for reliable links)
• Q = 7.94 → BER = 10-15 (exceeds most specifications)
• With RS-FEC (KR4), a raw BER of 10-4 can be corrected to <10-15.
• Q = 3.09 → BER = 10-3 (minimum for FEC to function)
• Q = 3.72 → BER = 10-4
• Q = 4.75 → BER = 10-6
• Q = 5.99 → BER = 10-9 (typical raw BER target without FEC)
• Q = 7.03 → BER = 10-12 (gold standard for reliable links)
• Q = 7.94 → BER = 10-15 (exceeds most specifications)
• With RS-FEC (KR4), a raw BER of 10-4 can be corrected to <10-15.
📋 Channel Loss Budget Calculator SI
Compute the signal-to-noise budget for a high-speed serial channel. Check pass/fail against a receiver sensitivity threshold.
Signal at RX = TX Amplitude − Connector Loss − Trace Loss − Via Loss − Crosstalk − Noise
Pass if Signal at RX ≥ Receiver Sensitivity
All values in mV. Typical 10 Gb/s channel: TX = 800 mV, total budget ~ 500 mV loss allowed.
Pass if Signal at RX ≥ Receiver Sensitivity
All values in mV. Typical 10 Gb/s channel: TX = 800 mV, total budget ~ 500 mV loss allowed.
Total Loss: --
Signal at Receiver: --
Margin: --
Budget Breakdown: Verdict: --
Signal at Receiver: --
Margin: --
Budget Breakdown: Verdict: --
Channel Budget Guidance:
• TX Amplitude: Typically 400-1000 mV for NRZ, 100-300 mV per level for PAM4.
• Connector Loss: ~1-3 dB per mated pair at Nyquist; SAS/QSFP connectors specified for 25+ Gbps.
• Trace Loss: Dominant contributor; depends on length, material (Df), frequency. FR-4: ~1 dB/in at 10 GHz.
• Via Loss: Each via transition adds 0.1-0.5 dB; back-drilling reduces stub resonance loss.
• Crosstalk: Can consume 10-20% of the budget in dense routing. Mitigate with spacing and layer planning.
• RX Sensitivity: Modern SerDes with DFE can recover signals as low as 25-50 mV after equalization.
• Always include a design margin of at least 3 dB (30%) for manufacturing variations and temperature effects.
• TX Amplitude: Typically 400-1000 mV for NRZ, 100-300 mV per level for PAM4.
• Connector Loss: ~1-3 dB per mated pair at Nyquist; SAS/QSFP connectors specified for 25+ Gbps.
• Trace Loss: Dominant contributor; depends on length, material (Df), frequency. FR-4: ~1 dB/in at 10 GHz.
• Via Loss: Each via transition adds 0.1-0.5 dB; back-drilling reduces stub resonance loss.
• Crosstalk: Can consume 10-20% of the budget in dense routing. Mitigate with spacing and layer planning.
• RX Sensitivity: Modern SerDes with DFE can recover signals as low as 25-50 mV after equalization.
• Always include a design margin of at least 3 dB (30%) for manufacturing variations and temperature effects.
🔎 Troubleshooting Decision Wizard Diag
Interactive decision tree for diagnosing Signal Integrity, Power Integrity, and EMI issues. Answer yes/no to narrow down the root cause.
Select a Problem Category
Choose the domain of the issue you are investigating:
How to Use the Wizard:
• Select a problem domain: Signal Integrity, Power Integrity, or EMI/EMC.
• Answer each yes/no question based on your observations and measurements.
• The wizard will narrow down to a specific diagnosis with actionable recommendations.
• Use the Back button to revise answers or Restart to begin a new investigation.
• Each path contains 5+ decision nodes covering the most common failure modes.
• SI path: Covers jitter, insertion loss, reflections, DDR timing, edge rates, and more.
• PI path: Covers ripple, switching noise, SSN, VRM response, ground bounce, and anti-resonance.
• EMI path: Covers clock harmonics, cable emissions, broadband noise, susceptibility, ESD, and conducted emissions.
• Select a problem domain: Signal Integrity, Power Integrity, or EMI/EMC.
• Answer each yes/no question based on your observations and measurements.
• The wizard will narrow down to a specific diagnosis with actionable recommendations.
• Use the Back button to revise answers or Restart to begin a new investigation.
• Each path contains 5+ decision nodes covering the most common failure modes.
• SI path: Covers jitter, insertion loss, reflections, DDR timing, edge rates, and more.
• PI path: Covers ripple, switching noise, SSN, VRM response, ground bounce, and anti-resonance.
• EMI path: Covers clock harmonics, cable emissions, broadband noise, susceptibility, ESD, and conducted emissions.
📚 Calculator Usage Reference
Quick reference for using these tools effectively in your design workflow.
Pre-Layout Phase
- Use Target Impedance to set PDN requirements
- Use Impedance Calculator to define stackup geometry
- Use Channel Budget to verify link feasibility
- Use Decoupling Optimizer to plan capacitor selection
Post-Layout Verification
- Use Crosstalk Estimator to check spacing rules
- Use Reflection Calculator to evaluate via transitions
- Use Eye Margin Explorer to predict link quality
- Use BER Estimator to set noise budgets
Debug & Troubleshooting
- Use Troubleshooting Wizard for systematic root-cause analysis
- Cross-reference measurements with calculator predictions
- Compare measured vs. expected impedance/loss values
- Iterate on the design using the calculators to predict improvement