A
Antenna Factor (AF)
A calibration parameter relating the electric field strength at an antenna to the voltage at the antenna terminals, expressed in dB/m. Used in EMI testing to convert measured voltages to field strengths.
Anti-pad
The clearance hole in a power or ground plane around a via or through-hole that is not connected to that plane. Anti-pad size affects via impedance and return path continuity.
Attenuation
The reduction in signal amplitude as it propagates through a transmission medium, typically expressed in dB per unit length. In PCBs, attenuation is caused by conductor loss (skin effect) and dielectric loss (Df).
Adaptive Equalization
An equalization technique used in high-speed SerDes receivers that automatically adjusts filter coefficients to compensate for varying channel loss and distortion, typically using LMS or sign-sign adaptation algorithms.
Aperture (EMC)
An opening or slot in a shielding enclosure through which electromagnetic energy can leak. Aperture radiation is significant when the aperture dimension approaches half a wavelength of the interfering signal.
AC Coupling Capacitor
A series capacitor placed in a high-speed serial link to block DC offset between transmitter and receiver. Typical values are 75-200 nF for multi-gigabit SerDes. Must have low ESR and ESL, and the RC time constant must be sized for the lowest data pattern frequency.
Annular Ring
The width of copper pad remaining around a drilled via hole after fabrication. Minimum annular ring is specified by IPC standards (typically 1-5 mils) and affects via reliability. Breakout (pad shifted off drill center) violates annular ring requirements.
Anti-Resonance
A peak in PDN impedance that occurs at the frequency where the impedance of a lower-value capacitor group transitions to the impedance of a higher-value group. The resulting parallel resonance creates an impedance spike that can exceed the target impedance and cause voltage ripple.
B
BER (Bit Error Rate)
The ratio of erroneously received bits to the total number of transmitted bits. A key metric for digital communication link quality. Typical targets: 10^-12 for SerDes links, 10^-15 for fiber optic links.
Bathtub Curve (BER)
A plot of BER vs. sampling point timing within the unit interval (UI). The curve is shaped like a bathtub, with low BER in the center (eye opening) and high BER at the edges where jitter causes bit errors.
Bypass Capacitor
A capacitor placed between power and ground near an IC to provide a low-impedance path for high-frequency current transients and to reduce power supply noise. Also called a decoupling capacitor.
Broadside Coupling
Electromagnetic coupling between traces on adjacent PCB layers that run parallel vertically (one directly above the other). Used in broadside-coupled differential pairs.
Bondwire Inductance
The parasitic inductance introduced by the wire bonds connecting an IC die to its package leads, typically 1-3 nH per bond wire. A major contributor to package-level signal integrity and power delivery issues.
BGA (Ball Grid Array)
An IC package type where solder balls arranged in a grid on the bottom of the package connect to the PCB. BGA escape routing, via-in-pad, and power/ground ball assignment significantly impact both signal and power integrity. Ball pitch ranges from 0.4 mm to 1.27 mm.
Back-Drilling
A PCB fabrication process that removes the unused stub portion of a through-hole via by drilling from the opposite side with a controlled-depth drill. Eliminates via stub resonances that cause insertion loss notches at high frequencies. Critical for 10+ Gbps designs.
Balun
A device that converts between balanced (differential) and unbalanced (single-ended) signal formats. Used in measurement setups, antenna interfaces, and test fixtures. Can be implemented as a transformer, transmission line structure, or active circuit.
C
CDR (Clock and Data Recovery)
A circuit in a SerDes receiver that extracts the clock signal from the incoming data stream and uses it to sample the data at the optimal point within each unit interval.
CISPR
Comite International Special des Perturbations Radioelectriques. An international organization that sets EMC standards. CISPR 32 covers emissions from multimedia equipment; CISPR 35 covers immunity.
Common-Mode Noise
Noise that appears equally on both conductors of a signal pair with respect to a reference (ground). Common-mode noise is a primary source of radiated EMI and is typically mitigated using common-mode chokes and balanced routing.
Conducted Emissions
Electromagnetic energy emitted by a device through its power and signal cables rather than radiated through the air. Measured per CISPR standards from 150 kHz to 30 MHz.
Crosstalk
Unwanted coupling of a signal from one trace (aggressor) to an adjacent trace (victim) through mutual capacitance and inductance. Measured as NEXT (near-end) and FEXT (far-end) crosstalk.
CTLE (Continuous Time Linear Equalizer)
An analog equalizer in a SerDes receiver that boosts high-frequency components of the received signal to compensate for frequency-dependent channel loss. Implemented as a programmable peaking amplifier.
Current Loop Area
The area enclosed by the signal current path and its return current path. A larger loop area acts as a more efficient antenna, increasing radiated EMI. Minimizing loop area is a fundamental EMC design principle.
Copper Weight
A measure of copper thickness on PCB layers, expressed in oz/ft2. Standard 1 oz copper is 1.4 mils (35 um) thick; 0.5 oz is 0.7 mils (17.5 um). Heavier copper (2-3 oz) is used for power layers requiring higher current capacity.
Characteristic Impedance
See Z0. The ratio of voltage to current for a wave traveling along a transmission line. Determined by trace geometry (width, height, thickness) and dielectric properties. Maintaining controlled impedance is fundamental to signal integrity.
Compliance Testing
The process of verifying that a product meets the electrical, EMI, and protocol requirements of a specific standard (USB, PCIe, HDMI, Ethernet). Includes transmitter output testing, receiver jitter tolerance, eye mask measurements, and protocol-layer verification.
Cavity Resonance
Standing-wave resonances formed between parallel conductive planes (power/ground) in a PCB, analogous to a rectangular waveguide cavity. Resonant frequencies depend on plane dimensions: f_mn = (c / (2*sqrt(Dk))) * sqrt((m/L)^2 + (n/W)^2). Causes impedance peaks in the PDN and can couple noise to sensitive circuits.
D
Decoupling Capacitor
A capacitor placed between power and ground planes near an IC to supply instantaneous current during switching transients and maintain low PDN impedance at high frequencies. Selection considers C, ESR, ESL, and SRF.
DFE (Decision Feedback Equalizer)
A non-linear equalizer in a SerDes receiver that uses previously decided bits to cancel intersymbol interference (ISI) from post-cursor reflections. Operates after the slicer, using feedback taps.
Dielectric Constant (Dk / Er)
The relative permittivity of an insulating material. Determines signal propagation velocity (v = c / sqrt(Dk)) and trace impedance. FR-4 has Dk ~ 4.2-4.5; low-loss materials range from 3.0-3.7.
Differential Pair
Two traces routed in close proximity that carry complementary signals (equal amplitude, opposite polarity). Provides common-mode noise rejection and reduces EMI. Differential impedance is typically 85-100 ohms.
Dissipation Factor (Df / tan delta)
A measure of dielectric loss in a PCB laminate material. Lower Df means less signal attenuation at high frequencies. FR-4: Df ~ 0.02; mid-loss: 0.005-0.01; ultra-low-loss: < 0.003.
Duty Cycle Distortion (DCD)
A form of deterministic jitter where the duration of logic-high and logic-low states are unequal. Caused by asymmetric rise/fall times or threshold offsets. Reduces timing margin in the eye diagram.
DDR (Double Data Rate)
A memory interface technology that transfers data on both the rising and falling edges of the clock signal, doubling throughput vs. SDR. DDR5 operates at 4800-8400 MT/s with 1.1V signaling. Requires precise impedance control, length matching, and power integrity for the VDDQ rail.
Differential Impedance
The impedance between the two conductors of a differential pair when driven with equal and opposite signals. Z_diff = 2 * Z_odd = 2 * Z0 * (1 - k), where k is the coupling coefficient. Typical targets: 85 ohms (USB), 100 ohms (PCIe, Ethernet).
De-embedding
A calibration technique that mathematically removes the effects of test fixtures, cables, and connectors from S-parameter measurements, isolating the DUT (device under test) response. Methods include TRL, AFR (automatic fixture removal), and port extension. Critical for accurate characterization of PCB vias, traces, and connectors.
DC Bias Derating
The reduction in effective capacitance of an MLCC when a DC voltage is applied across it, caused by the ferroelectric properties of the ceramic dielectric. A 10 uF X5R capacitor rated at 6.3V may lose 50-80% of its capacitance at 5V bias. Must be accounted for in PDN design by using higher-rated or larger components.
E
EMI (Electromagnetic Interference)
Unwanted electromagnetic energy that can disrupt the operation of electronic equipment. Sources include switching circuits, digital buses, and power converters. Controlled through shielding, filtering, and proper PCB layout.
EMC (Electromagnetic Compatibility)
The ability of electronic equipment to function satisfactorily in its electromagnetic environment without introducing intolerable electromagnetic disturbances to other equipment in that environment.
Eye Diagram
A visualization of a digital signal created by overlaying many unit intervals of a waveform. The resulting pattern resembles an eye, where the opening indicates signal quality. Height shows voltage margin; width shows timing margin.
ESR (Equivalent Series Resistance)
The effective resistance of a capacitor at a given frequency, representing all real (lossy) elements. ESR determines the minimum impedance a capacitor can achieve at its self-resonant frequency.
ESL (Equivalent Series Inductance)
The parasitic inductance inherent in a capacitor due to its leads, electrodes, and mounting. ESL determines the self-resonant frequency and limits the capacitor's effectiveness at high frequencies.
ESD (Electrostatic Discharge)
A sudden flow of static electricity between two objects at different electrical potentials. ESD can damage sensitive IC inputs and must be mitigated with TVS diodes, guard rings, and proper grounding at I/O interfaces.
Equalization
Signal processing techniques that compensate for frequency-dependent channel loss and distortion. Includes transmitter-side pre-emphasis/de-emphasis (FFE), receiver-side continuous-time linear equalization (CTLE), and decision feedback equalization (DFE). Essential for links exceeding 5 Gbps.
Effective Dielectric Constant (Dk_eff)
The weighted average dielectric constant experienced by electromagnetic fields on a microstrip trace, accounting for the portion of the field in air and the portion in the substrate. Dk_eff is always less than the material Dk for microstrip; for stripline, Dk_eff equals Dk.
F
FEC (Forward Error Correction)
An error-correction coding technique that adds redundancy to transmitted data, allowing the receiver to detect and correct bit errors without retransmission. Used in high-speed SerDes links (e.g., RS-FEC in 100GbE) to relax channel BER requirements.
Ferrite Bead
A passive component that provides frequency-dependent impedance, converting high-frequency noise energy into heat. Used in power supply filtering and EMI suppression. Characterized by impedance at 100 MHz, DC resistance, and rated current.
FEXT (Far-End Crosstalk)
Crosstalk noise measured at the far end of the victim trace (same end as the aggressor signal propagation). FEXT increases with coupled length and is proportional to the difference between capacitive and inductive coupling coefficients.
FR-4
The most common PCB laminate material, a glass-reinforced epoxy. Has Dk ~ 4.2-4.5 and Df ~ 0.02 at 1 GHz. Suitable for designs up to about 5-10 Gbps; higher speeds require low-loss alternatives.
Fly-by Topology
A routing topology used in DDR3/DDR4/DDR5 where clock and command/address signals daisy-chain through each DRAM device sequentially, rather than connecting in a star/T topology. Requires write leveling to compensate for propagation delay differences.
FFE (Feed-Forward Equalizer)
A transmitter-side linear equalizer that uses a tapped delay line with programmable coefficients to pre-compensate for channel loss. Pre-cursor and post-cursor taps cancel ISI before it accumulates in the channel. Also called TX FIR filter.
Fiber Weave Effect
See Glass Weave Effect. Variations in dielectric constant caused by the woven fiberglass structure of PCB laminates, which can cause impedance variations and differential pair skew. Particularly problematic when trace pitch aligns with glass bundle pitch.
G
Ground Bounce
A transient voltage fluctuation on the ground reference caused by di/dt current flowing through ground plane or package inductance when multiple outputs switch simultaneously. Also called simultaneous switching noise (SSN).
Ground Plane
A continuous copper layer in a PCB stackup that serves as the reference for signal return currents and provides shielding. Maintaining ground plane integrity (no splits or slots under signals) is essential for SI and EMI control.
Guard Trace
A grounded trace placed between signal traces to reduce crosstalk. Most effective when stitched to the ground plane with vias at regular intervals (every lambda/10 at the highest frequency of concern).
Glass Weave Effect
Local variations in dielectric constant caused by the non-uniform distribution of glass fibers in PCB laminate. Can cause intra-pair skew in differential signals and impedance variations. Mitigated with spread-glass or NE-glass materials.
Gasket (EMI)
A conductive material placed between mating surfaces of an EMI shield or enclosure to maintain shielding continuity at joints and seams. Types include knit wire mesh, beryllium copper fingers, conductive elastomers, and form-in-place gaskets. Must maintain contact force and conductivity over the product lifetime.
Gerber File
The standard file format (RS-274X or Gerber X2) used to describe each layer of a PCB design for manufacturing. Includes copper layers, solder mask, silkscreen, drill files, and board outline. Accurate Gerber output is critical; errors can result in incorrect impedance, missing pads, or fabrication defects.
H
Harmonic
An integer multiple of the fundamental frequency of a periodic signal. Digital clock signals contain significant energy at odd harmonics. EMI measurements must consider harmonics up to the bandwidth determined by the signal rise time.
HDMI (High-Definition Multimedia Interface)
A high-speed digital interface for audio/video transmission. HDMI 2.1 supports up to 48 Gbps using TMDS and FRL signaling. PCB design requires controlled differential impedance (100 ohm), length matching, and proper shielding.
High-Frequency Laminate
PCB substrate materials engineered for low dielectric loss at microwave and millimeter-wave frequencies. Examples include Rogers RO4003C, Isola I-Tera MT40, and Panasonic Megtron 6/7. Characterized by stable Dk and low Df (< 0.005).
Half-Power Bandwidth
The frequency range over which a filter, amplifier, or resonant structure delivers at least half its maximum power (-3 dB points). In PCB decoupling, the effective bandwidth of a capacitor extends from DC to approximately its SRF.
Heatsink Grounding
The practice of electrically connecting a metallic heatsink to ground to prevent it from acting as an unintentional antenna for EMI radiation. Without grounding, the heatsink can couple to switching noise from the IC and radiate efficiently at frequencies where its dimensions approach half a wavelength.
HDI (High Density Interconnect)
A PCB technology using microvias, fine lines/spaces (<75 um), and thin dielectrics to achieve higher wiring density per unit area. HDI stackups may include sequential lamination cycles with stacked or staggered microvias. Enables routing of fine-pitch BGA packages (0.4-0.65 mm ball pitch).
I
Impedance (Characteristic)
The ratio of voltage to current for a wave traveling in one direction on a transmission line, denoted Z0. Determined by trace geometry, dielectric properties, and stackup. Typical values: 50 ohms single-ended, 85-100 ohms differential.
Insertion Loss (S21/Sdd21)
The ratio of signal power at the output to signal power at the input of a channel, measured in dB. A key metric for channel quality. Includes conductor loss, dielectric loss, and impedance mismatch effects.
ISI (Intersymbol Interference)
Distortion of a data signal caused by energy from adjacent symbols spreading into the current symbol's time window, due to bandwidth-limited channels. Manifests as eye closure and is compensated with equalization (CTLE, DFE, FFE).
IPC-2141
An IPC standard providing design guidelines for impedance control of high-frequency circuits on printed boards. Includes formulas for microstrip, stripline, and differential pair impedance calculation.
Intra-Pair Skew
The time difference between the positive and negative signals of a differential pair, caused by length mismatch or dielectric variation (glass weave effect). Converts differential signal energy to common-mode noise.
Impedance Profile
A plot of impedance magnitude (and optionally phase) as a function of frequency for a PDN or transmission line. Generated from S-parameter measurements using a VNA, or from simulation. The PDN impedance profile must remain below the target impedance across all frequencies where significant current transients occur.
J
Jitter
The deviation of a signal's timing edges from their ideal positions. Decomposed into random jitter (RJ, Gaussian) and deterministic jitter (DJ, bounded). Total jitter at a given BER: TJ = DJ + 2 * N(BER) * RJ_rms.
Jitter Transfer Function
The frequency-domain response of a CDR/PLL to input jitter. Describes how much jitter at each frequency passes through the clock recovery circuit. Important for cascaded jitter analysis in multi-hop links.
JTAG (Joint Test Action Group)
IEEE 1149.1 standard for boundary scan testing. Provides serial access to IC I/O pins for board-level test and debug. Uses TCK, TMS, TDI, TDO signals. Signal integrity requirements are modest due to low data rates.
Jitter Tolerance
The maximum input jitter amplitude that a receiver can tolerate while maintaining the specified BER, expressed as a function of jitter frequency. A key compliance metric for SerDes receivers, defining the jitter rejection capability of the CDR loop.
K
Knee Frequency
The frequency above which the spectral content of a digital signal is negligible, approximately f_knee = 0.5 / t_rise. All design rules for trace lengths, decoupling, and plane resonances must consider frequencies up to the knee frequency.
Klopfenstein Taper
An optimum impedance-matching taper profile that provides equal-ripple return loss response over a defined bandwidth. Used in high-frequency PCB transitions (e.g., connector-to-trace) to minimize reflections.
KR-FEC (Clause 74 FEC)
A Reed-Solomon forward error correction scheme defined in IEEE 802.3, also known as RS(528,514). Corrects up to 7 symbol errors per frame. Used in 25GbE/100GbE links. Adds approximately 2.7% bandwidth overhead but allows operation at raw BER up to ~1e-4, correcting to <1e-12 post-FEC.
L
LISN (Line Impedance Stabilization Network)
A test fixture used in conducted emission measurements that provides a defined impedance (50 ohm) to the equipment under test at RF frequencies while allowing DC power to flow. Specified in CISPR 16-1-2.
Loss Tangent
The tangent of the dielectric loss angle, equal to the dissipation factor (Df). Represents the ratio of dielectric loss to stored energy. Directly determines signal attenuation in PCB traces at high frequencies.
LVDS (Low Voltage Differential Signaling)
A high-speed, low-power differential signaling standard (TIA/EIA-644) using 350 mV swing into 100-ohm termination. Supports data rates up to ~3.125 Gbps. Common in display interfaces and FPGA I/O.
Loop Inductance
The inductance of the complete current loop formed by the signal path and its return path. Lower loop inductance reduces voltage noise (V = L * di/dt) and EMI. Achieved by tight coupling between signal and return paths.
Latch-up
A destructive condition in CMOS ICs where a parasitic thyristor (PNPN structure) is triggered, creating a low-impedance path between power and ground. Caused by excessive undershoot below ground, overshoot above Vdd, or ESD events. Requires power cycling to recover and can permanently damage the device.
Lambda / 10 Rule
A design rule stating that PCB features (trace lengths, via spacings, guard trace stitching intervals) should be kept below one-tenth of the wavelength at the highest frequency of concern to prevent distributed effects and ensure lumped-circuit behavior.
Layer Transition
A signal route change from one PCB layer to another through a via. Each layer transition requires attention to reference plane continuity; if the reference plane changes, stitching vias must be placed nearby to provide a return current path and avoid EMI.
M
Microvia
A small-diameter via (typically 75-150 um drill) connecting only two adjacent layers, formed by laser drilling rather than mechanical drilling. Offers lower parasitic inductance and capacitance than through-hole vias. Stacked or staggered microvias enable high-density BGA escape routing.
Microstrip
A transmission line structure where a trace on an outer PCB layer is referenced to a ground plane beneath it through the dielectric. The effective dielectric constant is lower than the material Dk because part of the field propagates in air.
Mixed-Mode S-Parameters
S-parameters expressed in differential and common-mode basis (Sdd, Scc, Sdc, Scd) rather than single-ended. Sdd21 is differential insertion loss; Scd21 is mode conversion. Essential for analyzing differential pair performance.
MLCC (Multi-Layer Ceramic Capacitor)
The most common capacitor type for PCB decoupling, offering low ESL and small form factor. Available in values from 1 pF to 100 uF. Subject to DC bias derating and piezoelectric effects (acoustic noise).
Mode Conversion
The unwanted conversion of differential-mode signals to common-mode signals (or vice versa) caused by asymmetry in a differential channel (length mismatch, impedance imbalance, via asymmetry). Measured by Scd21 parameter.
Mounting Inductance
The parasitic inductance added to a capacitor by its PCB mounting pads, vias, and traces. Can be larger than the capacitor's inherent ESL. Minimized by using wide, short traces, via-in-pad, and multiple vias per pad. Reverse-geometry capacitors (wide termination) also reduce mounting inductance.
Megtron (Panasonic)
A family of low-loss PCB laminates manufactured by Panasonic. Megtron 6 (Dk ~ 3.4, Df ~ 0.002 at 10 GHz) is widely used for 25-56 Gbps SerDes channels. Megtron 7 offers even lower loss for 112 Gbps PAM4 applications. Provides significantly better performance than FR-4 at frequencies above 5 GHz.
N
NEXT (Near-End Crosstalk)
Crosstalk noise measured at the near end of the victim trace (same end as the aggressor driver). NEXT saturates once the coupled length exceeds the critical length (L_crit = t_rise * v_prop / 2). Caused by the sum of capacitive and inductive coupling.
Nyquist Frequency
Half the data rate (in NRZ signaling) or half the symbol rate. Represents the fundamental frequency component of the data signal. Channel insertion loss at Nyquist is a key specification for SerDes link design.
NRZ (Non-Return-to-Zero)
A binary signaling scheme where the signal level represents a 0 or 1 for the entire bit period. The simplest modulation scheme. Nyquist frequency equals half the bit rate. Used in SerDes links up to ~28 Gbps.
Near-Field Probe
A small electromagnetic probe used to localize EMI sources on a PCB. H-field probes (loop) detect magnetic fields from current flow; E-field probes (monopole) detect voltage-related electric fields.
Noise Floor
The level of background noise below which a signal cannot be detected. In EMC measurements, the noise floor is determined by the spectrum analyzer's sensitivity and the ambient electromagnetic environment. In SerDes links, the noise floor sets the minimum achievable BER.
Notch Filter (EMI)
A narrow bandstop filter used to attenuate a specific interfering frequency while passing all others. In EMI mitigation, notch filters can target a specific clock harmonic that exceeds the regulatory limit. Implemented with LC tank circuits or distributed resonant structures.
Notch (Insertion Loss)
A sharp dip in the insertion loss (S21) frequency response caused by a resonant structure such as a via stub, unterminated trace, or plane cavity. The notch frequency is determined by the stub length and dielectric constant. Degrades signal integrity at the affected frequencies.
O
ODT (On-Die Termination)
Termination resistors integrated into a DRAM or controller IC die, eliminating the need for discrete termination components. ODT values are programmable (e.g., 34, 40, 48, 60, 120 ohms in DDR4) and can be enabled/disabled dynamically.
Open-Short-Load (OSL) Calibration
A VNA calibration technique using three known standards (open, short, and matched load) to remove systematic measurement errors from S-parameter data. Essential for accurate impedance and loss measurements.
Overshoot
The peak voltage excursion of a signal above its intended high-level voltage after a rising transition. Caused by impedance mismatches and insufficient termination. Excessive overshoot can violate absolute maximum ratings and damage ICs.
OATS (Open Area Test Site)
A standardized outdoor or semi-anechoic test facility for measuring radiated emissions from electronic equipment. An OATS must meet site attenuation requirements per CISPR 16-1-4 and provide a conductive ground plane with a turntable and variable-height antenna mast.
P
PAM4 (Pulse Amplitude Modulation 4-Level)
A signaling scheme that encodes 2 bits per symbol using 4 voltage levels, doubling throughput vs. NRZ at the same baud rate. Used in 56+ Gbps SerDes. Requires 9.5 dB more SNR than NRZ for the same BER, making equalization and FEC critical.
PCIe (PCI Express)
A high-speed serial bus standard for chip-to-chip and board-to-board communication. PCIe 5.0 runs at 32 GT/s NRZ; PCIe 6.0 uses PAM4 at 64 GT/s. Requires controlled impedance (85 ohm differential), low loss, and strict length matching.
PDN (Power Distribution Network)
The complete network delivering power from the voltage regulator to IC power pins, including planes, vias, traces, and decoupling capacitors. PDN impedance must stay below the target impedance across the frequency range of interest.
Power Integrity (PI)
The discipline of ensuring clean, stable power delivery to all IC loads on a PCB. Involves target impedance analysis, decoupling strategy, plane resonance management, and VRM stability analysis.
Propagation Delay
The time for a signal to travel from one point to another on a transmission line. For FR-4 microstrip: ~145-165 ps/in; for stripline: ~170-180 ps/in. Determined by Dk and geometry.
Pre-emphasis / De-emphasis
A transmitter equalization technique that boosts high-frequency content of the signal by increasing transition amplitudes relative to sustained levels, compensating for frequency-dependent channel loss.
PRBS (Pseudo-Random Binary Sequence)
A deterministic bit pattern generated by a linear feedback shift register that approximates random data with known statistical properties. Common patterns: PRBS-7 (127 bits), PRBS-15, PRBS-23, PRBS-31. Used in SerDes compliance testing and BER measurement. Longer PRBS patterns stress the DFE and CDR more severely.
Plane Resonance
Standing-wave resonances that occur in power/ground plane pairs at frequencies where the plane dimensions equal half-wavelength multiples. Causes peaks in PDN impedance. Damped with strategically placed decoupling capacitors and resistive termination at plane edges.
PLL (Phase-Locked Loop)
A feedback control circuit that generates an output signal whose phase is locked to the phase of a reference signal. Used in SerDes for clock generation and data recovery. PLL bandwidth, phase noise, and jitter peaking directly affect link timing margin.
Q
Q Factor
In BER analysis, Q = eye_height / (2 * sigma_noise), relating signal amplitude to noise. Q = 7 corresponds to BER = 10^-12. In resonant circuits, Q = f_center / bandwidth, indicating sharpness of resonance. Higher Q means less damping.
Quasi-Peak Detector
A weighted measurement detector used in EMC emissions testing that responds to both amplitude and repetition rate of signals. QP readings are between peak and average values and correlate with perceived interference to communications.
QSFP (Quad Small Form-factor Pluggable)
A compact, hot-pluggable transceiver module used for high-speed networking. QSFP28 supports 4x25 Gbps (100GbE); QSFP56 supports 4x56 Gbps (200GbE); QSFP-DD supports 8x56 Gbps (400GbE). PCB design requires careful channel loss management and connector-to-via transition optimization.
R
Radiated Emissions
Electromagnetic energy emitted from a device through free space. Measured in an anechoic chamber or OATS per CISPR 32 standards, from 30 MHz to several GHz. Controlled through PCB layout, shielding, filtering, and cable management.
Reflection Coefficient (Gamma)
The ratio of reflected signal amplitude to incident signal amplitude at an impedance discontinuity. Gamma = (ZL - Z0) / (ZL + Z0). A value of 0 indicates a perfect match; +1 is an open circuit; -1 is a short circuit.
Return Loss
The ratio of incident power to reflected power at a port, expressed in dB: RL = -20*log10(|Gamma|). Higher return loss indicates a better impedance match. Typical specs: > 10 dB for connectors, > 15 dB for PCB vias.
Return Path
The path taken by the return current of a signal, typically through the nearest reference plane. At low frequencies, return current follows the path of least resistance; at high frequencies, it follows the path of least inductance (directly beneath the signal trace).
Rise Time
The time for a signal to transition from 20% to 80% (or 10% to 90%) of its final value. Determines the bandwidth of the signal: BW ~ 0.35 / t_rise. Faster rise times require more careful impedance control and EMI management.
Roughness (Copper)
The microscopic surface texture of copper foil in PCBs, characterized by Rz (peak-to-valley roughness). Standard electrodeposited copper has Rz of 5-10 um; HVLP (hyper-very-low-profile) foil has Rz < 3 um. Surface roughness increases conductor loss at high frequencies through increased effective path length and skin effect enhancement.
Ringing
Oscillatory behavior on a signal waveform caused by reflections at impedance discontinuities. The frequency and amplitude of ringing depend on the mismatch magnitude and the round-trip delay of the transmission line. Terminated properly, ringing is eliminated or damped within 1-2 round trips.
S
S-Parameters (Scattering Parameters)
Frequency-domain characterization of a network describing how RF energy scatters at its ports. S11 = input return loss, S21 = insertion loss/gain, S12 = reverse isolation, S22 = output return loss. Measured with a VNA.
SerDes (Serializer/Deserializer)
A transceiver that converts parallel data to a serial stream for transmission over a high-speed differential link and back to parallel at the receiver. Modern SerDes support 56-112+ Gbps per lane with PAM4 modulation.
Signal Integrity (SI)
The discipline of ensuring electrical signals maintain acceptable quality (voltage levels, timing, noise margins) as they propagate through the physical channel. Encompasses impedance control, crosstalk, attenuation, and equalization.
Skin Effect
The tendency of high-frequency current to flow in a thin layer near the conductor surface. Skin depth decreases with frequency: delta = sqrt(2 * rho / (omega * mu)). At 1 GHz in copper, skin depth is about 2.1 um. Increases conductor resistance and loss at high frequencies.
Spread Spectrum Clocking (SSC)
A technique that modulates the clock frequency by a small amount (typically 0.5-1.5%) to spread the spectral energy over a wider bandwidth, reducing peak emissions by 6-10 dB. Used in PCIe, SATA, USB, and other standards to meet EMI requirements.
Stackup
The arrangement of copper and dielectric layers in a PCB. Defines impedance, coupling, and reference plane assignment. A well-designed stackup maintains continuous reference planes, controls impedance, and minimizes EMI.
Stripline
A transmission line structure where the trace is embedded between two reference planes within the PCB. Provides better shielding and lower EMI than microstrip, but has higher loss and tighter impedance control requirements.
Stub
An unterminated branch or via section that creates a resonant discontinuity. Via stubs resonate at f = c / (4 * L_stub * sqrt(Dk)), causing notches in insertion loss. Back-drilling removes via stubs in high-speed designs.
SRF (Self-Resonant Frequency)
The frequency at which a capacitor's impedance reaches its minimum (ESR). Below SRF, the component is capacitive; above SRF, it becomes inductive. SRF = 1 / (2 * pi * sqrt(C * ESL)). Decoupling is only effective below the SRF.
Shielding Effectiveness (SE)
The ratio of electromagnetic field strength without and with a shield, expressed in dB: SE = 20*log10(E_incident / E_transmitted). Depends on reflection loss, absorption loss, and aperture leakage. A well-designed metallic enclosure provides 40-80 dB of shielding effectiveness.
Stitching Via
A via connecting ground planes on different PCB layers to ensure low-impedance return current paths and maintain ground plane continuity. Placed near signal vias during layer transitions, at plane splits, and along board edges to control EMI. Spacing should not exceed lambda/20 at the highest frequency of concern.
SSC (Spread Spectrum Clocking)
See Spread Spectrum Clocking. A frequency modulation technique applied to clock signals that spreads spectral energy over a wider bandwidth, reducing peak emissions by 6-10 dB. Down-spread modulates below the nominal frequency; center-spread modulates symmetrically above and below.
T
Target Impedance
The maximum allowable PDN impedance to keep voltage ripple within specification: Z_target = V_dd * ripple% / I_transient. The PDN must stay below target impedance from DC to the highest frequency of concern.
TDR (Time Domain Reflectometry)
A measurement technique that sends a fast step pulse into a transmission line and analyzes reflections to characterize impedance variations along the line. Used to locate impedance discontinuities, measure trace impedance, and debug SI issues.
Transmission Line
A conductor structure that must be treated as a distributed circuit (not lumped) when its electrical length is a significant fraction of the signal wavelength. Rule of thumb: treat as transmission line when trace length > lambda/10 or length > rise_time * v_prop / 6.
TVS Diode (Transient Voltage Suppressor)
A semiconductor device that clamps transient overvoltages (ESD, lightning, inductive spikes) to a safe level. Available in unidirectional and bidirectional types. Key specs: breakdown voltage, clamping voltage, peak current rating, and capacitance.
Trace Width
The width of a copper conductor on a PCB, a primary factor in determining characteristic impedance and current-carrying capacity. Wider traces have lower impedance, lower resistance, and can carry more current. Calculated using IPC-2152 for current and IPC-2141 for impedance.
Termination
A resistive element placed at the end of a transmission line to absorb the signal and prevent reflections. Common schemes: series (source) termination, parallel (end) termination, AC termination, Thevenin termination, and on-die termination (ODT). Proper termination is essential for signal integrity.
TDT (Time Domain Transmission)
A measurement technique complementary to TDR that measures the signal transmitted through a device under test rather than the reflected signal. Provides information about insertion loss, propagation delay, and rise time degradation of the channel.
TLP (Transmission Line Pulse)
A test method used to characterize the ESD robustness of devices by applying controlled rectangular current pulses with nanosecond rise times. Provides I-V curves that reveal clamping voltage, holding voltage, and failure current of protection structures.
Thermal Via
A via designed primarily for heat conduction from a surface component pad to an internal copper plane or the opposite side of the PCB. Arrays of thermal vias under power pads significantly improve thermal performance. Must balance thermal conductivity against solder wicking concerns.
U
UI (Unit Interval)
The time duration of one symbol (bit) in a serial data stream. UI = 1 / data_rate. For 10 Gbps NRZ, 1 UI = 100 ps. Eye width is measured in UI and must be sufficient for reliable sampling by the CDR.
USB (Universal Serial Bus)
A widely-used serial communication standard. USB 3.2 Gen 2x2 supports 20 Gbps; USB4 supports 40-80 Gbps. High-speed USB requires 90-ohm differential impedance, controlled skew, and proper termination.
Undershoot
The peak voltage excursion of a signal below its intended low-level voltage (or below ground) after a falling transition. Like overshoot, caused by impedance mismatches. Can cause latch-up in CMOS devices if it exceeds the substrate diode threshold.
USB Type-C
A reversible connector standard supporting USB 3.2, USB4, Thunderbolt 3/4, DisplayPort Alt Mode, and USB Power Delivery (up to 240W). The 24-pin connector requires careful PCB design with controlled impedance for SuperSpeed pairs (90 ohm differential), CC pin configuration, and proper shielding.
V
VNA (Vector Network Analyzer)
A precision instrument that measures S-parameters of a device under test by transmitting a known signal and measuring magnitude and phase of reflected and transmitted signals. Essential for characterizing channels, connectors, vias, and PCB structures.
VSWR (Voltage Standing Wave Ratio)
The ratio of maximum to minimum voltage amplitude on a transmission line due to reflections: VSWR = (1 + |Gamma|) / (1 - |Gamma|). A VSWR of 1:1 is a perfect match. Connectors are typically specified with VSWR < 1.5:1.
Via
A plated hole in a PCB connecting traces on different layers. Types include through-hole, blind, buried, and microvias. Via parasitics (inductance, capacitance, stub resonance) degrade signal integrity at high frequencies.
Via Stub
The unused portion of a through-hole via below the signal layer connection. Acts as an unterminated transmission line stub, causing destructive resonance at f = c / (4 * stub_length * sqrt(Dk)). Removed by back-drilling in high-speed designs.
VRM (Voltage Regulator Module)
A DC-DC converter that provides regulated supply voltage to a load (CPU, FPGA, etc.). VRM output impedance, transient response, and bandwidth determine low-frequency PDN performance. Typically dominates PDN impedance below 100 kHz.
W
3W Rule
A PCB routing guideline stating that the center-to-center spacing between traces should be at least 3 times the trace width (3W) to reduce crosstalk to approximately 70% of its maximum. The 5W rule provides further reduction for sensitive signals.
Wave Impedance
The ratio of the electric field to the magnetic field of an electromagnetic wave. In free space, wave impedance is 377 ohms. Near a source, the wave impedance depends on whether the source is predominantly electric (high Z) or magnetic (low Z).
Write Leveling
A training procedure in DDR3/4/5 that aligns the DQS strobe timing at each DRAM device to compensate for the flight-time differences inherent in the fly-by command/address/clock topology.
X
X-Capacitor
A safety-rated capacitor connected between line and neutral in an AC power filter to suppress differential-mode conducted noise. Rated for continuous connection across mains voltage (X1: 4 kV surge, X2: 2.5 kV surge).
XAUI (10 Gigabit Attachment Unit Interface)
A 4-lane serial interface running at 3.125 Gbps per lane (12.5 Gbps aggregate) used for 10 GbE chip-to-chip connections. Uses 8b/10b encoding. Largely superseded by higher-speed SerDes interfaces.
X2Y Capacitor
A patented multi-layer capacitor structure with integrated common-mode and differential-mode filtering in a single component. Features extremely low ESL (~50 pH) due to internal cancellation of current loop inductance. Effective for high-frequency decoupling and EMI filtering up to several GHz.
Y
Y-Capacitor
A safety-rated capacitor connected between a power line and chassis ground in an AC power filter to suppress common-mode conducted noise. Limited to small values (typically 1-4.7 nF) to restrict ground leakage current for safety compliance.
Yagi Antenna
A directional antenna used as a reference in EMC testing for calculating antenna gain and performing site attenuation measurements. Its well-characterized gain pattern makes it useful for validating test site performance.
Y-Parameter
Admittance parameters that describe the input-output relationship of an electrical network in terms of current response to applied voltages. Related to S-parameters through mathematical conversion. Used in some PDN analysis tools for parallel network calculations.
Wavelength
The physical distance covered by one complete cycle of an electromagnetic wave: lambda = c / (f * sqrt(Dk_eff)). At 10 GHz in FR-4 microstrip (Dk_eff ~ 3.3), lambda is approximately 16.5 mm. Transmission line effects become significant when trace length exceeds lambda/10.
Z
Zero-Crossing Jitter
Jitter measured at the signal threshold crossing point (typically Vdd/2 for single-ended, 0 V for differential). Includes all jitter sources: random, deterministic, periodic, data-dependent, and duty-cycle distortion components.
Zoning (EMC)
The practice of partitioning a PCB into functional zones (analog, digital, power, RF, I/O) to contain noise within each zone and prevent coupling between sensitive and noisy circuits. Zone boundaries are defined by ground plane segmentation, filtering, and physical separation.
Z0 (Characteristic Impedance)
The impedance that a transmission line presents to a traveling wave, determined by the per-unit-length inductance and capacitance: Z0 = sqrt(L/C). For a lossless line, Z0 is purely real. Standard values are 50 ohms (single-ended) and 100 ohms (differential).
Zdiff (Differential Impedance)
The impedance measured between the two conductors of a differential pair: Zdiff = 2 * Z0 * (1 - k), where k is the coupling coefficient. Tightly coupled pairs have lower Zdiff. Standard values: 85 ohms (USB 2.0), 90 ohms (USB 3.x), 100 ohms (PCIe, Ethernet, HDMI).
Zodd (Odd-Mode Impedance)
The impedance of one conductor in a coupled pair when driven with equal and opposite signals (differential mode). Z_odd = Z0 * (1 - k) where k is the coupling coefficient. Differential impedance equals 2 * Z_odd. Coupled traces have Z_odd less than the uncoupled Z0.
Zeven (Even-Mode Impedance)
The impedance of one conductor in a coupled pair when both conductors are driven with identical signals (common mode). Z_even = Z0 * (1 + k). Common-mode impedance equals Z_even / 2. Important for analyzing mode conversion and common-mode noise behavior.
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