Grand Final Capstone: Integrated System Design
A high-speed board featuring DDR4 + PCIe Gen3 + Gigabit Ethernet. Solve SI, PI, SerDes, and EMI challenges to earn your certification badge. Every choice matters -- the domains are interconnected.
System Overview
Your board contains the following subsystems. Each presents unique SI/PI/EMI challenges that interact.
Processor
1.0V core, 50A
1.8V I/O, 5A
BGA-1156
DDR4 (x2 DIMMs)
3200 MT/s
64-bit bus
1.2V VDDQ
PCIe Gen3 x4
8 GT/s per lane
Backplane connector
12-inch traces
Gigabit Ethernet
1000BASE-T PHY
RJ45 + Magnetics
25 MHz RefClk
System Specifications
| Subsystem | Key Spec | Target |
|---|---|---|
| PCIe Gen3 | Eye Height | > 120 mV |
| PCIe Gen3 | Eye Width | > 0.6 UI |
| Processor PDN | Impedance | < 0.6 mOhm |
| Processor PDN | Ripple | < 3% (30 mV) |
| DDR4 SerDes | Eye Mask | Pass |
| System EMI | Radiated | FCC Class B |
1 SI Challenge: Fix the PCIe Eye Diagram
The PCIe Gen3 x4 link fails eye mask compliance. The current design uses long microstrip traces with no equalization and poor via design. Fix the channel to pass.
2 PI Challenge: Meet PDN Impedance Target
The processor PDN must maintain impedance below 0.6 mOhm from DC to 500 MHz. The current design has anti-resonance peaks. Select capacitors to flatten the impedance.
3 SerDes Compliance: Pass DDR4 Eye Mask
The DDR4 3200 MT/s interface must pass write/read eye mask. Tune ODT, slew rate, and length matching to achieve compliance.
4 EMI Challenge: Reduce Radiated Emissions
The system fails FCC Class B radiated emissions at several frequencies. Apply EMI mitigation techniques to pass compliance.
Final Scoring
Run the comprehensive system-level compliance check across all four domains.
System Compliance Report
Signal Integrity
Power Integrity
SerDes / DDR4
EMI Compliance
HW Design Masterclass -- Certified
You have demonstrated proficiency in Signal Integrity, Power Integrity, SerDes Design, and EMI Compliance. You are certified to design high-speed digital systems.