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Track 15: SI + PI + EMI Interaction

Signal Integrity, Power Integrity, and EMI are deeply coupled. A PDN resonance can degrade an eye diagram. A reflection on a signal trace can create common-mode current that radiates. This track shows how these three domains interact and why holistic design is essential.

1. SI Causing EMI: Reflections Create Common-Mode Radiation

When a signal reflects due to impedance mismatch, differential-to-common-mode conversion occurs at asymmetries. This common-mode current radiates efficiently as EMI.

Signal with Reflections
Radiated Emission (CM Current)
30%
20 ps
Reflection: -- dB | CM Current: -- mA | Estimated E-field @ 3m: -- dBuV/m
Key Insight: Even 10% impedance mismatch combined with 20ps pair skew can generate common-mode currents exceeding FCC Class B limits. Proper termination and length matching are both SI and EMI requirements.

2. PI Causing Jitter: Supply Noise Modulates Timing

Power supply noise modulates the threshold voltage and propagation delay of CMOS gates, creating periodic jitter (Pj) that closes the eye diagram.

PDN Voltage Ripple
Eye Diagram (with Jitter)
30 mV
50 MHz
Ripple %Vdd: -- % | Induced Pj: -- ps | Eye Width Reduction: -- %
Key Insight: Supply ripple of 5% of Vdd can induce 15-30ps of periodic jitter in high-speed I/O. At 10 Gbps (100ps UI), this consumes 15-30% of the timing budget. PDN design is inseparable from SI timing closure.

3. Return Path Discontinuity = Slot Antenna

When a signal trace crosses a split in the reference plane, the return current must detour around the gap. This creates a slot antenna that radiates efficiently.

5 mm
500 MHz
10 mA
Slot Length: -- mm | Resonant Freq: -- GHz | Radiation @ 3m: -- dBuV/m | FCC Limit: 40 dBuV/m
Key Insight: A 30mm slot in a ground plane resonates near 5 GHz and can radiate 10-20 dB above FCC limits. Never route high-speed signals across plane splits. Stitch vias and bridge capacitors are essential when splits are unavoidable.

4. PDN Noise Degrades Eye Opening

Supply ripple adds directly to the signal as amplitude noise, reducing the vertical eye opening and degrading the voltage margin.

PDN Impedance vs Frequency
Eye Diagram
20 mOhm
60 mOhm
5 A
Voltage Noise: -- mV | Eye Height Reduction: -- % | Pass/Fail: --

5. Integrated Exercise: Identify the SI/PI/EMI Problem

For each scenario, identify whether the root cause is an SI, PI, or EMI problem.

Scenario A

A 10 Gbps SerDes link shows excessive BER. The eye diagram reveals the eye height is reduced but eye width is acceptable. The issue worsens when the processor load increases.

Scenario B

Radiated emission testing fails at 750 MHz. The board has DDR4 running at 1.5 GHz data rate. Investigation shows the DDR signal crosses a power plane split to reach a via field.

Scenario C

A clock signal at the receiver shows 25ps of periodic jitter at 100 MHz. The power rail measurement shows 40mV ripple at the same 100 MHz frequency.

Scenario D

A USB 3.0 link fails compliance testing. The eye diagram shows both reduced height AND reduced width. TDR measurement shows Z0 = 78 ohms (target: 90 ohms differential).

Scenario E

A system passes all SI and EMI tests at room temperature but fails radiated emissions at 85C. Analysis reveals the PDN impedance peak shifts due to capacitor ESR increase at high temperature, exciting a cavity resonance.

Track 15 Quiz: SI + PI + EMI Interaction

Q1: How does impedance mismatch on a differential pair create EMI?

Q2: Why does PDN noise create jitter?

Q3: A signal trace crosses a plane split. What is the primary EMI mechanism?

Q4: Increasing PDN impedance above target primarily affects the eye diagram by:

Q5: Which design approach best addresses SI + PI + EMI simultaneously?