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Track 16: Debugging & Case Studies

Real-world debugging requires systematic approaches and pattern recognition. This track presents compliance debug flowcharts, failure case studies, redesign examples, and interactive "What Went Wrong?" exercises to build debugging intuition.

1. Compliance Debug Process: Radiated Emissions

Follow this systematic flowchart when your product fails radiated emissions testing.

RE Test FAIL Identify Failing Frequencies (Compare to clock harmonics) Clock Harmonic? YES Check spread spectrum clocking Add SSC, reduce rise time, shield Check return path continuity Ensure no plane splits crossed NO Check PDN resonances Measure PDN Z vs frequency PDN Peak? YES Add decoupling / stitch vias Target anti-resonance freq NO Check cables & connectors Common-mode chokes, ferrites Check shielding effectiveness Gaps, seams, apertures Apply Fixes and Retest Iterate until all frequencies pass with margin

2. SI Failure Debug: Eye Diagram Case Studies

Case Study A: PCIe Gen3 Link Fails at Receiver

Symptoms: Eye height reduced to 50mV (spec: 120mV min). Eye width OK. BER > 1e-8.

Root Cause: Via stub of 8 mils creating resonant null at 4.5 GHz, right at Nyquist for 8 GT/s.

Fix: Back-drill vias to reduce stub length to < 2 mils. Eye height recovered to 180mV.

Case Study B: DDR4 Fails Write Leveling at 3200 MT/s

Symptoms: DQ eye shows severe ISI with eye closure. Signals ring for 2 UI after transitions.

Root Cause: 15mm trace length mismatch between DQ and DQS within byte lane. ODT misconfigured (240 ohm instead of 34 ohm).

Fix: Correct ODT to 34 ohm, reduce length mismatch to < 2mm. Clean eye with 200ps margin.

Case Study C: 25G Ethernet SFP+ Link Marginal

Symptoms: Eye diagram shows excessive jitter (>0.3 UI). Jitter tracks a 156.25 MHz pattern.

Root Cause: Reference clock coupled into data lane through inadequate isolation (only 4mm spacing, shared via field).

Fix: Increase spacing to 15mm, add ground via fence between clock and data. Jitter reduced to 0.08 UI.

3. PI Failure Analysis: Power Delivery Case Studies

Case Study A: FPGA Fails During High-Activity Modes

Symptoms: VCC_INT drops by 120mV during burst activity. FPGA resets randomly. Scope shows 200MHz ringing.

Root Cause: Anti-resonance between bulk caps (4.7uF) and MLCC (100nF) at 200MHz. PDN impedance peak of 500 mOhm at that frequency.

Fix: Added 10nF caps to bridge the anti-resonance gap. Peak impedance reduced to 30 mOhm. Droop reduced to 25mV.

Case Study B: GPU Power Rail Shows Excessive Ripple

Symptoms: 1.0V rail shows 80mV ripple at 500 kHz switching frequency. GPU throttles under load.

Root Cause: VRM output inductor placed 25mm from GPU BGA. Long power trace adds 2nH inductance. Only 2x 22uF bulk caps near GPU.

Fix: Relocated VRM within 10mm of GPU. Added 4x 100uF bulk caps and 20x 100nF MLCC. Ripple reduced to 15mV.

Case Study C: DDR4 VTT Reference Voltage Noise

Symptoms: VTT (0.6V) shows 50mV noise correlated with burst reads. DDR4 DQ signals show asymmetric eye.

Root Cause: VTT regulator has 100mOhm output impedance at DDR switching frequency. 4 DIMM slots share single VTT source with 40mm trace runs.

Fix: Added local 100nF decoupling at each DIMM slot VTT pin. Used wider VTT distribution traces. Noise reduced to 8mV.

4. PCB Redesign Examples

Before/after comparisons showing how targeted PCB changes resolve SI/PI/EMI issues.

Before: High-Speed Routing (Rev A)
  • PCIe traces routed on layer 1 (microstrip)
  • Traces cross 3 plane splits
  • No length matching (30mm skew)
  • Via stubs: 60 mil
  • No ground via stitching

Result: Eye closed, EMI fail at 2.5GHz, 4GHz

After: High-Speed Routing (Rev B)
  • PCIe traces on layer 3 (stripline)
  • Continuous reference plane, no splits crossed
  • Length matched within 0.5mm
  • Via back-drilling, stub < 5 mil
  • Ground via fence on both sides

Result: Clean eye, 6dB EMI margin

Before: PDN Layout (Rev A)
  • VRM 40mm from processor
  • 12x 100nF MLCC, 2x 22uF bulk
  • Caps placed on back side only
  • 2 power vias per cap pad
  • No embedded capacitance consideration

Result: 150mV droop, anti-resonance at 50MHz

After: PDN Layout (Rev B)
  • VRM within 15mm of processor
  • 40x 100nF + 10x 10nF + 4x 100uF
  • Caps on both sides, interleaved values
  • 8 power vias per cap, wide power shapes
  • Thin dielectric for embedded capacitance

Result: 20mV droop, flat impedance to 500MHz

Before: EMI Containment (Rev A)
  • I/O connectors grounded with single via
  • No common-mode chokes on cables
  • Board edge traces within 3mm of edge
  • No ground stitching around board perimeter
  • Crystal oscillator near board edge

Result: Failed FCC Class B at 6 frequencies

After: EMI Containment (Rev B)
  • 360-degree ground pad on all I/O connectors
  • CM chokes on USB, HDMI, Ethernet
  • 20mm keep-out from board edge
  • Ground via fence at 200mil pitch around perimeter
  • Crystal moved to board center, shielded

Result: Passed FCC Class B with 8dB margin

5. Troubleshooting Flowcharts

SI Debug Flowchart

SI Issue Detected Eye Height OK? NO Check: Loss, ISI, crosstalk, PDN noise YES Eye Width OK? NO Check: Jitter, reflections, supply noise YES PASS TDR measurement VNA S-params Apply fix: Termination / EQ / Layout

EMI Debug Flowchart

EMI Failure Identify failing freq bands Source = Clock? YES SSC / rise time / shielding NO Near-field probe to locate Fix: Planes / vias / chokes Retest with 6dB margin target

6. "What Went Wrong?" Interactive Scenarios

Click each scenario to reveal the answer and explanation.

Scenario 1: USB 3.0 device fails SuperSpeed enumeration but USB 2.0 works fine. ▶

What Went Wrong: The USB 3.0 differential pair was routed on layer 1 (microstrip) with no ground via stitching and crossed a power plane split. The return path discontinuity created a common-mode conversion that destroyed the 5 GHz signal quality.

Fix: Rerouted USB 3.0 on inner stripline layer, added ground via fence, ensured continuous reference plane. Device enumerated at SuperSpeed immediately.

Scenario 2: DDR4 memory works at 2400 MT/s but fails at 3200 MT/s on 2 of 4 byte lanes. ▶

What Went Wrong: The two failing byte lanes had DQ-to-DQS length mismatch of 12mm (within spec at 2400 but out of spec at 3200). Additionally, the ODT values were optimized for 2400 and too weak for 3200 MT/s operation.

Fix: Reduced length mismatch to 1mm, updated ODT to 48 ohm for write and 40 ohm for read. All byte lanes passed at 3200 MT/s.

Scenario 3: Product passes EMI at room temperature but fails at 85C ambient. ▶

What Went Wrong: The MLCC decoupling capacitors lost 40% of their capacitance at high temperature (X5R ceramic, DC bias + temperature derating). This shifted the PDN anti-resonance into the frequency range of the switching regulator, creating a cavity resonance that radiated.

Fix: Replaced X5R caps with C0G (NPO) for critical locations. Added additional X7R caps with higher nominal values to compensate for derating. Passed at all temperatures.

Scenario 4: PCIe Gen3 link shows bathtub curve with barely passing BER at one end of the trace. ▶

What Went Wrong: The PCB via at the receiver end had an 8-mil stub (12-layer board, signal on layer 3, via goes to layer 12). The stub resonance at 4.6 GHz created a notch in S21 exactly at the Nyquist frequency of 8 GT/s PCIe Gen3.

Fix: Implemented via back-drilling to reduce stub to 2 mils. S21 improved by 4dB at Nyquist. BER improved from 1e-9 to < 1e-15.

Scenario 5: Ethernet PHY passes all tests on bench but intermittently drops packets in the system. ▶

What Went Wrong: The 25 MHz crystal oscillator for the Ethernet PHY was placed near a switching regulator. The 500 kHz switching noise modulated the reference clock, creating 200 Hz of periodic jitter. While small in absolute terms, this jitter accumulated in the PLL, causing occasional packet loss when combined with cable loss.

Fix: Relocated crystal 20mm away from the switcher, added ground via ring around crystal area, and added an LC filter on the power supply to the crystal driver. Zero packet loss thereafter.

Track 16 Quiz: Debugging & Case Studies

Q1: The first step in debugging a radiated emissions failure should be:

Q2: A via stub creates a resonant null in S21 at approximately:

Q3: An anti-resonance in the PDN impedance is caused by:

Q4: When a near-field probe localizes EMI to a specific connector, the most effective first fix is:

Q5: X5R MLCC capacitors lose significant capacitance due to: