PCB Stackup Design

The PCB stackup is the foundation of every high-speed and EMC-compliant design. It determines impedance control, return current quality, crosstalk isolation, and radiated emissions performance. A poor stackup cannot be compensated for by clever routing; it must be correct from the start.

Why Stackup Matters

The stackup directly affects the following critical parameters:

• Impedance Control - Trace width-to-dielectric height ratio sets characteristic impedance
• Return Current Quality - Adjacent planes provide low-inductance return paths
• Crosstalk Isolation - Tightly coupled signal-plane pairs reduce far-end crosstalk
• EMI Performance - Plane pairs act as bypass capacitors; broken returns radiate
• Power Integrity - Closely spaced power-ground pairs lower PDN impedance
• Manufacturability - Symmetric stackups prevent warping during lamination

Common Stackup Configurations

4-Layer Stackup Guidelines

The 4-layer board is the minimum for any design requiring controlled impedance. The preferred arrangement is:

Interactive Stackup Designer

Use this tool to build and visualize a PCB stackup. Add or remove layers, assign types, set thicknesses, and see the total board height update in real time.

Controlled Impedance

Controlled impedance is the practice of designing PCB traces so that their characteristic impedance matches the system impedance (commonly 50 ohm single-ended or 100 ohm differential). This requires precise relationships between trace width, dielectric thickness, dielectric constant, and copper thickness.

Microstrip Geometry

A microstrip is a trace on an outer layer of the PCB, referenced to a plane on the adjacent inner layer. It is partially embedded in the dielectric substrate and partially exposed to air.

Stripline Geometry

A stripline is a trace on an inner layer, sandwiched between two reference planes. It is fully embedded in the dielectric and offers better shielding and lower radiation than microstrip.

Interactive Impedance Calculator

Common Impedance Targets

Return Current Paths

Every signal current has a return current. Understanding where return currents flow is arguably the single most important concept in PCB EMC design. The path of the return current depends on frequency.

Low Frequency vs. High Frequency Behavior

Return Current Under a Trace (High Frequency)

The following animation illustrates how at high frequencies, return current flows directly under the signal trace in the adjacent reference plane, creating a tightly coupled transmission line:

Plane Discontinuity Problem

When a signal trace crosses a gap, slot, or split in its reference plane, the return current must detour around the discontinuity. This creates a large loop area that radiates like an antenna.

Reference Plane Transitions

When a signal via transitions from one layer to another, the return current must also change planes. Without stitching vias nearby, the return current must find an alternate (longer) path.

Grounding Strategies

Grounding is the most debated and most misunderstood topic in EMC. The right strategy depends on the frequency range, circuit type, and system architecture.

Single-Point vs. Multi-Point Grounding

Star Ground Topology

A star ground provides a single common connection point for multiple circuit sections. It is effective for mixed-signal designs where analog and digital ground currents must not share paths.

Ground Plane Splits

Ground plane splits are sometimes used to isolate sensitive circuits, but they are dangerous if not handled properly. A split plane forces return currents to find alternate paths, which can dramatically increase EMI.

Grounding Decision Matrix

Chassis Grounding

The PCB ground plane must connect to the chassis (enclosure) ground for EMC compliance. This connection provides a path for common-mode currents to flow to the enclosure rather than radiating.

Component Placement Strategy

Component placement is the second most critical step in PCB design (after stackup). Good placement makes routing easier, reduces EMI, and improves signal integrity. Poor placement cannot be fixed by clever routing.

Decoupling Capacitor Placement

Clock Source Placement

Clock sources (oscillators, PLLs, clock buffers) are the primary sources of radiated emissions. They must be placed with care.

• Place clock sources near their loads to minimize trace length
• Keep clock traces away from board edges (at least 3x trace width from edge)
• Route clock traces on inner layers (stripline) when possible for shielding
• Surround clock oscillator cans with ground vias to reduce radiation
• Isolate clock regions from sensitive analog circuits

Connector Placement

General Placement Rules

High-Speed Routing Techniques

High-speed routing is where signal integrity theory meets physical implementation. Every routing decision affects impedance, timing, crosstalk, and EMI.

Length Matching

Many high-speed interfaces (DDR, parallel buses) require signals within a group to arrive at the receiver at the same time. This requires matching the electrical lengths of all traces in the group.

Serpentine (Meander) Routing

Serpentine traces are used to add length to shorter traces for matching. However, they must be designed carefully to avoid self-coupling.

BGA Breakout Routing

Ball Grid Array (BGA) packages require careful escape routing due to the dense pin grid. The breakout strategy depends on ball pitch and layer count.

Via Transitions

When a trace transitions from one layer to another through a via, the change in geometry creates an impedance discontinuity. Minimize the impact with these techniques:

• Use the smallest practical via size to reduce capacitive loading
• Place ground return vias adjacent to signal vias when changing reference planes
• Use back-drilled vias to eliminate stubs on through-hole vias (see Via Discontinuities section)
• Use pad and antipad sizes optimized for impedance (larger antipad = less capacitance)

General High-Speed Routing Rules

Differential Pair Design

Differential signaling is the dominant method for high-speed data transfer (USB, PCIe, HDMI, Ethernet, SATA). It provides superior noise immunity, lower EMI, and enables higher data rates than single-ended signaling.

Edge-Coupled vs. Broadside-Coupled

Edge-Coupled Microstrip Cross-Section

Differential Pair Routing Rules

Skew and Mode Conversion

When the two traces of a differential pair have different lengths (skew), part of the differential signal converts to common-mode noise. Common-mode signals radiate much more efficiently than differential signals.

Via Discontinuities

Vias are necessary for layer transitions but introduce parasitic inductance, capacitance, and potentially resonant stubs. At high data rates (10+ Gbps), via design becomes a critical performance factor.

Via Equivalent Circuit

A through-hole via can be modeled as a series inductance with shunt capacitance to the reference planes it passes through:

Via Stub Effect

When a signal enters a through-hole via on one layer and exits on another, the remaining via barrel beyond the exit layer acts as an unterminated stub. This stub creates a resonance that causes signal attenuation at the quarter-wave frequency.

Back-Drilling

Back-drilling (also called controlled-depth drilling) mechanically removes the unused stub portion of a through-hole via. This is the most common technique for eliminating via stubs in high-speed designs.

Via Design Guidelines

Via Technology Comparison

PCB Design Review Checklist

Use this checklist before releasing your PCB design for fabrication. Click each item to mark it as reviewed. A thorough design review catches problems that are expensive or impossible to fix after manufacturing.

Stackup and Layer Assignment

Impedance Control

Return Currents and Grounding

Decoupling and Power Integrity

Signal Integrity

EMC and Compliance

Manufacturing

Track 3 Quiz: PCB Design for SI/PI/EMI

Test your understanding of PCB design principles. Select the best answer for each question, then click "Check Answers" at the bottom to see your score.