Track 5: Harmonics & Digital Signals

Digital signals are not single-frequency sinusoids. Every clock, data line, and switching waveform is a composite of many harmonics. Understanding the harmonic structure of digital signals is essential for both signal integrity and EMI compliance. This track takes you from Fourier fundamentals all the way to practical harmonic control techniques.

1. Harmonics Fundamentals

Jean-Baptiste Joseph Fourier proved that any periodic waveform can be decomposed into a sum of sinusoids. For hardware engineers, this is the single most important concept linking time-domain signals to frequency-domain behavior.

Fourier Series of a Square Wave

An ideal 50% duty-cycle square wave of amplitude A and fundamental frequency f₀ is composed entirely of odd harmonics:

x(t) = (4A/π) × [ sin(2πf₀t) + (1/3)sin(6πf₀t) + (1/5)sin(10πf₀t) + ... ]

x(t) = (4A/π) Σ_n=1,3,5... (1/n) sin(2πnf₀t)

Key Insight: A perfect square wave has infinite bandwidth. Every odd harmonic (3rd, 5th, 7th, ...) contributes to the sharp edges. The more harmonics you include, the sharper the transitions become.

The amplitude of each harmonic decreases as 1/n. The fundamental has amplitude 4A/π, the 3rd harmonic has amplitude 4A/(3π), the 5th has 4A/(5π), and so on. In dB terms, the harmonics roll off at 20 dB/decade.

Interactive: Building a Square Wave from Harmonics

Use the slider below to add harmonics one by one. Watch how the composite waveform approaches a square wave as more harmonics are included. The spectrum bars on the right show the amplitude of each harmonic.

Number of Harmonics: 1

Time Domain - Waveform Synthesis

Frequency Domain - Spectrum

Gibbs Phenomenon

Even with many harmonics, you will notice overshoot and ringing near the transitions. This is called the Gibbs phenomenon - the overshoot converges to about 9% of the step height and never disappears, no matter how many harmonics are summed. This is not just a mathematical curiosity; it has real implications for signal integrity.

Harmonics Included	Waveform Quality	Bandwidth
1 (fundamental only)	Pure sine wave	1 × f₀
1-3	Rounded trapezoid	3 × f₀
1-7	Recognizable square wave	7 × f₀
1-15	Good square wave with ripple	15 × f₀
1-39	Excellent with Gibbs overshoot	39 × f₀

2. Rise/Fall Time Effects on Spectrum

Real digital signals do not have infinitely fast edges. The rise time (t_r) and fall time (t_f) of a signal determine how quickly its spectral envelope rolls off at high frequencies. This is arguably the most important concept for EMI engineering.

The Bandwidth-Rise Time Relationship

BW = 0.35 / t_r

where BW is the 3dB bandwidth in Hz and t_r is the 10%-90% rise time in seconds.

This tells us the effective bandwidth of a trapezoidal signal. Beyond this frequency, the spectral energy falls off rapidly.

Spectral Envelope of a Trapezoidal Wave

The spectrum of a trapezoidal waveform has two distinct regions:

Below f₁ = 1/(π × T): Harmonics are relatively flat (0 dB/decade slope for the envelope).
Between f₁ and f₂ = 1/(π × t_r): Envelope rolls off at -20 dB/decade.
Above f₂: Envelope rolls off at -40 dB/decade.

Key Insight: The -20 dB/dec to -40 dB/dec transition frequency is controlled entirely by rise time. Slower rise times push this corner frequency lower, reducing high-frequency emissions dramatically. Doubling the rise time reduces EMI at high frequencies by 6 dB.

Interactive: Rise Time vs Spectral Envelope

Adjust the rise time slider to see how the spectral envelope changes. The green dashed line shows the -20 dB/dec region, and the red dashed line shows the -40 dB/dec rolloff region.

Rise Time (t_r): 1.0 ns

Clock Frequency: 100 MHz

Rise Time vs EMI Impact

Rise Time	BW (0.35/t_r)	Relative EMI at 1 GHz
0.1 ns	3.5 GHz	Baseline (0 dB)
0.5 ns	700 MHz	-14 dB
1.0 ns	350 MHz	-20 dB
2.0 ns	175 MHz	-26 dB
5.0 ns	70 MHz	-34 dB

Practical Warning: While slowing rise times reduces EMI, it also degrades signal integrity. Slower edges increase susceptibility to crosstalk and reduce timing margins. The optimal rise time is a tradeoff between EMI and SI requirements.

3. Clock Signal Spectra

Clock signals are periodic and therefore have the strongest, most predictable harmonic content of any digital signal. They are typically the dominant source of EMI in a digital system.

Duty Cycle Effects

The duty cycle (D) of a clock signal determines which harmonics are present:

50% duty cycle: Only odd harmonics (1f, 3f, 5f, ...). Even harmonics are zero.
Non-50% duty cycle: All harmonics present. The amplitude of the n-th harmonic is proportional to |sin(nπD) / (nπ)|.
25% or 75% duty cycle: Every 4th harmonic is zero.
33% duty cycle: Every 3rd harmonic is zero.

|c_n| = (2A/nπ) × |sin(nπD)|

where D = duty cycle (0 to 1), A = amplitude, n = harmonic number

Interactive: Clock Spectrum Analyzer

Adjust the clock frequency, duty cycle, and rise time to see the resulting spectrum. Blue bars show harmonic amplitudes. The orange envelope shows the theoretical rolloff.

Clock Frequency: 100 MHz

Duty Cycle: 50%

Rise Time: 0.5 ns

Why Clocks Dominate EMI

Clock signals are the primary EMI concern because:

They are perfectly periodic, concentrating all energy into narrow spectral lines.
They run continuously (unlike data which may be intermittent).
Even tiny imbalances in routing or loading create common-mode currents.
Their harmonics extend well into the GHz range where radiation efficiency is high.

4. Harmonics and Signal Integrity

Signal integrity depends on preserving enough harmonic content to maintain waveform fidelity. The channel between driver and receiver acts as a low-pass filter, attenuating higher harmonics.

Bandwidth Requirements for Digital Signals

A rule of thumb: to preserve a digital waveform with acceptable fidelity, the channel must pass harmonics up to approximately:

BW_min ≈ 0.35 / t_r (for 10-90% rise time)
BW_min ≈ 0.22 / t_r (for 20-80% rise time)

What Happens When Harmonics Are Filtered?

Harmonics Preserved	Signal Effect	Eye Diagram Impact
Up to 5th harmonic	Recognizable but rounded edges	Open eye, reduced margins
Up to 3rd harmonic	Significantly rounded, overshoot possible	Reduced eye height and width
Fundamental only	Sinusoidal - no useful digital information in NRZ	Eye nearly closed for NRZ
Phase distortion on harmonics	Asymmetric rise/fall, jitter	Horizontal eye closure

Channel Loss and Harmonics

PCB traces, connectors, and vias all attenuate higher harmonics more than lower ones. This frequency-dependent loss causes:

Inter-symbol interference (ISI): Energy from one bit period bleeds into the next because high-frequency components that define sharp transitions are lost.
Rise time degradation: The received signal has slower edges than the transmitted signal.
Jitter: If different harmonics experience different group delays, the signal timing shifts unpredictably.

The SI-EMI Tradeoff: Signal integrity wants to preserve harmonics (fast edges, wide bandwidth). EMI compliance wants to suppress harmonics (slow edges, narrow bandwidth). Good hardware design finds the minimum bandwidth needed for reliable signaling and suppresses everything above that.

Equalization: Restoring Harmonics

Modern high-speed SerDes use equalization to compensate for channel loss:

CTLE (Continuous-Time Linear Equalizer): Boosts high-frequency harmonics at the receiver.
FFE (Feed-Forward Equalizer): Pre-emphasizes high frequencies at the transmitter.
DFE (Decision Feedback Equalizer): Removes ISI from previously decided bits.

These techniques effectively restore the harmonic content needed for signal fidelity, but they also restore high-frequency energy that can radiate. Careful PCB design must contain this energy.

5. Harmonics and EMI

EMI compliance testing measures radiated and conducted emissions across a wide frequency range. Digital signal harmonics are the primary source of these emissions.

Why Harmonics Cause EMI Failures

A 100 MHz clock has harmonics at 300 MHz, 500 MHz, 700 MHz, 900 MHz, 1.1 GHz, and so on. Even though each higher harmonic is weaker, several factors can cause high-frequency harmonics to exceed emission limits:

Antenna efficiency increases with frequency: A PCB trace or cable becomes a more efficient antenna at higher frequencies (radiation ∝ f²).
Resonances: Structural resonances in enclosures, cables, or PCB planes can amplify specific harmonics by 20-40 dB.
Common-mode currents: Even microamps of common-mode current on a cable can fail emissions tests at GHz frequencies.

Real-World Failure Mode: A 50 MHz clock with 0.3 ns rise times was passing CISPR 22 Class B at all frequencies except 750 MHz (15th harmonic). The cause: a cable resonance at 750 MHz amplified a tiny common-mode current by 30 dB.

CISPR Emission Limits

The most common regulatory standards for digital equipment emissions are CISPR 32 (replacing CISPR 22) and FCC Part 15. These define limits for:

Standard	Class	Environment	Limit (30-230 MHz)	Limit (230-1000 MHz)
CISPR 32 / FCC	Class A	Industrial	40 dBμV/m @ 10m	47 dBμV/m @ 10m
CISPR 32 / FCC	Class B	Residential	30 dBμV/m @ 10m	37 dBμV/m @ 10m

Class B limits are 10 dB stricter than Class A. Meeting Class B is the target for consumer products and is significantly more challenging.

The EMI Budget

To predict whether a harmonic will pass or fail, engineers create an EMI budget:

E_radiated = V_harmonic + G_antenna - L_shielding - L_filtering

Pass/Fail: E_radiated < CISPR Limit - Margin (typically 6 dB)

6 dB Margin Rule: Always design for at least 6 dB of margin below the regulatory limit. Production variation, temperature effects, and measurement uncertainty can easily account for 3-6 dB of variation.

6. Harmonic Control Techniques

There are several proven techniques to reduce harmonic emissions while maintaining signal integrity.

6.1 Rise Time Control

The most direct way to reduce high-frequency harmonics. Methods include:

Slew rate limiting: Many modern ICs offer programmable drive strength and slew rate. Use the slowest slew rate that meets timing requirements.
Series resistors: Adding a small series resistor (10-33 ohms) at the driver output slows the edge by forming an RC filter with the load capacitance.
Ferrite beads: Provide frequency-dependent impedance that primarily affects high-frequency harmonics while passing the fundamental relatively unattenuated.

6.2 Spread Spectrum Clocking (SSC)

Spread spectrum clocking deliberately modulates the clock frequency by a small amount (typically +/-0.5% to +/-1.5%), spreading each harmonic's energy across a wider bandwidth. This reduces the peak amplitude measured by an EMI receiver.

SSC Parameter	Typical Value	Effect on EMI
Modulation depth	±0.5%	~6 dB reduction
Modulation depth	±1.0%	~10 dB reduction
Modulation depth	±1.5%	~12 dB reduction
Modulation frequency	30-60 kHz	Must be > RBW of EMI receiver
Modulation profile	Triangular (Hershey-kiss)	Optimal spectral spreading

SSC Limitations: Spread spectrum clocking adds jitter to the clock, which may not be acceptable for high-speed serial links (PCIe, USB 3.x) or video interfaces. Always check the protocol specification for SSC compatibility. Most modern protocols do support SSC with specific parameters.

6.3 Filtering

Filtering can be applied at several points in the signal path:

Source filtering: RC or LC filters at the clock output.
Connector filtering: Common-mode chokes and capacitor arrays at I/O connectors.
Cable filtering: Ferrite cores on cables suppress common-mode harmonics.

6.4 Layout Techniques

Minimize loop area: Every signal-return loop is a radiating antenna. Keep signal and return paths close together.
Continuous ground planes: Provide the lowest-inductance return path, minimizing loop area.
Clock trace routing: Route clocks on inner layers sandwiched between ground planes for maximum shielding.
Guard traces: Grounded guard traces beside clock lines reduce near-field coupling.
Length matching: For differential clocks, match trace lengths to prevent common-mode conversion.

6.5 Shielding

When filtering and layout techniques are insufficient, shielding provides the last line of defense:

Board-level shields: Metal cans soldered over high-frequency circuits.
System enclosure: Metal or metalized plastic enclosure with proper gasket sealing.
Aperture control: Any opening in a shield must be much smaller than λ/20 at the highest frequency of concern.

Defense in Depth: The best EMI designs use multiple techniques in combination. Relying on a single technique creates fragile designs. A good approach: (1) slow edges where possible, (2) filter at connectors, (3) use SSC on clocks, (4) implement good layout, (5) add shielding as needed.

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