Track 6: Power Integrity Masterclass

Power integrity (PI) is the discipline of ensuring that every transistor in a system receives clean, stable power at the right voltage. Poor power integrity causes logic errors, excessive jitter, degraded signal integrity, and EMI failures. This track covers the entire power delivery network from VRM to on-die capacitance, with interactive tools to build intuition.

1. PDN Fundamentals

The Power Delivery Network (PDN) is the complete electrical path from the voltage regulator module (VRM) to the transistors on-die. It is a complex, distributed impedance network that must deliver current at very high slew rates while maintaining voltage within tight tolerances.

The PDN Hierarchy

A modern PDN consists of several stages, each responsible for a different frequency range:

PDN Impedance Profile

The goal of PDN design is to maintain impedance below a target impedance across all frequencies where the IC draws transient current. Each stage of the PDN is optimized for a specific frequency range:

PDN Stage	Frequency Range	Key Components	Limiting Factor
VRM	DC to ~10 kHz	Switching regulator + output capacitors	Control loop bandwidth
Bulk capacitors	10 kHz to 1 MHz	Polymer/electrolytic capacitors	ESR and ESL
MLCC decoupling	1 MHz to 500 MHz	Ceramic capacitors (X5R, X7R)	Mounting inductance
PCB planes	100 MHz to 1 GHz	Power/ground plane pair	Plane spreading inductance
On-die capacitance	> 500 MHz	IC intrinsic gate capacitance	Package inductance

Key Insight: The PDN is only as good as its weakest link. If any frequency band has impedance above the target, the voltage will droop or ring when current transients excite that frequency. The handoff between PDN stages is where problems typically occur.

2. Target Impedance

Target impedance is the maximum allowable PDN impedance at any frequency. If the PDN impedance exceeds this value, the supply voltage will deviate beyond the specified tolerance when the IC draws transient current.

Z_target = (V_dd × Ripple%) / ΔI

where:
V_dd = supply voltage (V)
Ripple% = allowed voltage ripple as a fraction (e.g., 0.05 for 5%)
ΔI = maximum transient current step (A)

For example, a 1.0V core supply with 5% tolerance and 10A transient current requires:

Z_target = (1.0 × 0.05) / 10 = 5 mΩ

Maintaining 5 milliohms across a wide frequency range is extremely challenging and requires careful design at every stage of the PDN.

Interactive Target Impedance Calculator

Target Impedance Calculator

Supply Voltage V_dd (V):

Allowed Ripple (%):

Transient Current ΔI (A):

% of IC current that is transient:

Z_target = -- mΩ

Target Impedance Trends

As supply voltages decrease and current demands increase, target impedance becomes progressively more difficult to achieve:

Era	V_dd	Typical ΔI	Ripple	Z_target
2005	1.8 V	5 A	5%	18 mΩ
2010	1.2 V	15 A	5%	4 mΩ
2015	1.0 V	30 A	3%	1 mΩ
2020+	0.8 V	50 A	2%	0.32 mΩ

Challenge: Sub-milliohm target impedances are nearly impossible to achieve with board-level components alone. Modern processors use integrated voltage regulators (IVR), embedded capacitors in the package substrate, and on-die power management to meet these extreme requirements.

3. Decoupling Capacitors

Decoupling capacitors are the workhorses of the PDN. They store charge locally and release it when the IC demands transient current, preventing the supply voltage from drooping during current spikes.

Real Capacitor Model: ESR, ESL, SRF

A real capacitor is not an ideal capacitance. It has parasitic resistance (ESR) and inductance (ESL) that fundamentally limit its high-frequency performance:

Z_cap(f) = ESR + j(2πf × ESL - 1/(2πf × C))

|Z_cap| = √(ESR² + (2πf×ESL - 1/(2πf×C))²)

SRF = 1 / (2π × √(ESL × C))

Below SRF: Capacitor behaves capacitively (impedance decreases with frequency)
At SRF: Impedance reaches minimum = ESR
Above SRF: Capacitor behaves inductively (impedance increases with frequency)

Interactive: Capacitor Impedance vs Frequency

Adjust the capacitor parameters to see how ESR and ESL affect the impedance curve. Use "Add Cap" to combine multiple capacitors in parallel and see the combined impedance.

Capacitance: 1 uF

ESR: 10 mΩ

ESL (mounted): 1.0 nH

Bank: 0 caps

Decoupling Best Practices

Practice	Why
Place caps as close to IC pins as possible	Minimizes mounting inductance (ESL)
Use via-in-pad or adjacent vias	Reduces connection inductance by ~50%
Mix capacitor values	Each value covers a different frequency range
Use smallest available package (0201, 01005)	Smaller package = lower ESL
Avoid excessively large capacitors	Large values have lower SRF, may not help at high frequencies

4. Anti-Resonance

When two capacitors of different values are placed in parallel, an anti-resonance peak can occur at a frequency between their individual self-resonant frequencies. At this frequency, the impedance of the parallel combination can actually be higher than either capacitor alone.

What Causes Anti-Resonance?

Anti-resonance occurs when one capacitor is operating in its inductive region (above its SRF) while the other is still in its capacitive region (below its SRF). The inductive impedance of one combines with the capacitive impedance of the other to form a parallel LC resonance.

f_anti-res ≈ between SRF_{large cap} and SRF_{small cap}

Z_peak can be 10× to 100× higher than the individual ESR values

Anti-Resonance Visualization

ESR Damping Factor: 1.0x

Mitigation Strategies

Increase ESR: Higher ESR damps the anti-resonance peak. Use the slider above to see the effect. Some designers deliberately use higher-ESR caps in the PDN.
Overlap SRF ranges: Use capacitor values that have closely-spaced SRFs so the anti-resonance is small.
Use many values: Three or more different capacitor values spread out the resonances and reduce individual peak heights.
Add resistance: Small series resistors (resistive decoupling) can flatten the impedance profile at the cost of slightly higher average impedance.

5. Ground Bounce

Ground bounce (also called simultaneous switching output noise or SSO) occurs when fast current transients flow through the parasitic inductance of the ground connections (pins, bond wires, vias). The voltage on the IC's internal ground shifts relative to the board ground.

V_bounce = L_eff × dI/dt

where L_eff = effective inductance of the ground path (typically 1-10 nH)
dI/dt = rate of change of current through the ground connection

Animated: Ground Bounce Mechanism

Ground Bounce Magnitude

Scenario	L_eff	dI/dt	V_bounce
1 output, 2 nH, moderate edge	2 nH	50 mA / 1 ns	100 mV
8 outputs, 2 nH, fast edge	2 nH	400 mA / 0.5 ns	1.6 V
32 outputs, 5 nH, fast edge	5 nH	1.6 A / 0.3 ns	26.7 V (!)

Critical: The third scenario shows why modern packages use hundreds of power/ground pins. A single ground pin with 5 nH of inductance simply cannot handle the transient current of 32 simultaneously switching outputs. BGA packages with dense ground pin arrays are essential for high-speed designs.

Reducing Ground Bounce

Use more power/ground pins (reduces effective inductance via parallelism).
Slow down output edge rates when possible.
Stagger output switching (avoid simultaneous transitions).
Use differential signaling (equal and opposite currents cancel ground bounce).
Place decoupling caps directly at power/ground pin pairs.

6. Simultaneous Switching Noise (SSN)

SSN is the generalized form of ground bounce that includes both power supply bounce and ground bounce. When many outputs or internal circuits switch simultaneously, the total current transient can be enormous.

SSN Components

V_SSN = N × L_eff × (dI_{per_driver} / dt)

where N = number of simultaneously switching drivers

SSN manifests in several ways:

Power rail collapse: V_dd droops when many gates switch high, drawing current through inductive power connections.
Ground lift: The internal ground rises when many gates switch low, pushing current back through inductive ground connections.
Quiet line noise: Non-switching outputs experience noise because they share the same power and ground network. A quiet output at logic "0" may momentarily appear as logic "1" due to ground lift.

SSN and Signal Integrity

SSN directly degrades signal integrity:

SSN Effect	SI Consequence	Mitigation
Ground lift on driver	Reduced output voltage swing	More ground pins
Ground lift on receiver	Shifted input threshold	Differential signaling
V_dd droop on driver	Slower rise time, reduced swing	Better decoupling
Time-varying ground shift	Jitter on signal edges	Isolated power domains

Design Rule: For buses wider than 8 bits, always calculate worst-case SSN assuming all outputs switch simultaneously with the same polarity. Compare the resulting voltage shift to the noise margin of the receiver. If SSN exceeds 30% of the noise margin, redesign the power delivery or output staging.

7. IR Drop

IR drop is the DC voltage loss across the resistance of power planes, traces, and vias between the VRM and the IC. While PDN impedance analysis focuses on AC behavior, the DC resistance can cause significant static voltage reduction, especially in high-current designs.

V_drop = I_load × R_path

R_plane = (ρ / t) × (L / W) = R_sq × (L / W)

where ρ = resistivity, t = copper thickness, L = path length, W = path width
R_sq = sheet resistance (mΩ/square)

Interactive IR Drop Calculator

IR Drop Calculator

Load Current (A):

Copper Thickness (oz):

Path Length (mm):

Path Width (mm):

V_drop = -- mV

Copper Thickness Reference

Copper Weight	Thickness	Sheet Resistance	Typical Use
0.5 oz	17.5 um	0.98 mΩ/sq	Signal layers
1 oz	35 um	0.49 mΩ/sq	Standard planes
2 oz	70 um	0.25 mΩ/sq	Power planes
3 oz	105 um	0.16 mΩ/sq	High-current designs

Practical Note: IR drop analysis should include vias. Each via has resistance on the order of 0.5-2 mΩ depending on drill size and plating thickness. For 10A flowing through a single via, this can mean 5-20 mV of drop per via.

8. Plane Resonance

A power/ground plane pair forms a parallel plate cavity resonator. At certain frequencies, standing waves form between the planes, creating regions of very high impedance. This can cause localized power integrity failures and EMI radiation from board edges.

f_mn = (c / (2√ε_r)) × √((m/a)² + (n/b)²)

where a, b = plane dimensions, m, n = mode indices (0,1,2,...), c = speed of light, ε_r = dielectric constant

Animated: Standing Wave Patterns

Mode m: 1

Mode n: 0

Board length a (mm): 200 mm

Board width b (mm): 150 mm

Plane Resonance Mitigation

Closely-spaced planes: Reducing the dielectric thickness between power and ground planes increases the interplane capacitance and damps resonances. 2-4 mil spacing is recommended for high-speed designs.
Decoupling capacitors at edges: Placing capacitors along board edges damps the resonant modes.
Lossy dielectrics: Higher-loss dielectrics at the plane boundary damp resonances (but increase signal loss on adjacent layers).
Stitching vias: Dense ground vias around the board perimeter reduce edge radiation.
Embedded capacitance materials: Special thin laminate materials (2 mil or less) between power/ground planes provide distributed capacitance that suppresses resonances.

9. PI-SI Interaction

Power integrity and signal integrity are not independent disciplines. Supply noise directly affects signal quality, and understanding this interaction is essential for high-speed design.

How Supply Noise Affects Signals

Output voltage modulation: When V_dd droops, the output driver produces a smaller voltage swing. When V_dd bounces high, it produces a larger swing. This creates data-dependent jitter.
Threshold shift: Ground bounce at the receiver shifts the effective input threshold, potentially causing bit errors.
Power supply induced jitter (PSIJ): Periodic supply noise at frequency f_noise creates jitter sidebands at ±f_noise around the data frequency.

PSIJ ≈ (V_noise / V_dd) × t_r

where V_noise = peak supply noise voltage
V_dd = nominal supply voltage
t_r = signal rise time

Eye Diagram Degradation

Supply noise affects both the vertical and horizontal dimensions of the eye diagram:

Supply Noise Type	Eye Diagram Effect	Severity
Random V_dd noise	Vertical eye closure (amplitude noise)	Moderate
Periodic V_dd ripple	Both vertical and horizontal closure (jitter)	High
Ground bounce	Asymmetric eye closure, threshold shift	High
SSN correlated with data	Data-dependent jitter, ISI-like effects	Very High

Modern Approach: State-of-the-art SI analysis includes the PDN impedance in the simulation. Tools like Ansys SIwave, Cadence Sigrity, and Keysight PathWave perform combined PI-SI simulation. The PDN S-parameter model is connected to the driver model, and supply noise is injected during transient simulation to accurately predict eye diagram degradation.

PI-SI Co-Design Guidelines

Simulate PDN impedance and verify target impedance compliance before finalizing the stackup.
Include PDN noise in SI simulations for any interface running above 5 Gbps.
Separate analog, digital, and high-speed power domains to prevent cross-coupling.
Budget jitter contributions: allocate a portion of the total jitter budget to PSIJ and verify through PI simulation.
Measure actual supply noise during prototype validation using near-field probes or dedicated test points.

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