Track 9: SerDes Compliance Labs - HW Design Masterclass

1. Channel Compliance

Insertion Loss Budgets

Channel insertion loss (IL) is the most fundamental compliance metric for high-speed serial links. It quantifies how much the channel attenuates the signal as a function of frequency. Insertion loss is measured as the S21 parameter (forward transmission coefficient) of the channel's S-parameter model.

Each standard defines a maximum insertion loss limit, typically specified at the Nyquist frequency (half the data rate). Beyond the Nyquist frequency, the signal content decreases but higher harmonics still affect eye quality.

Standard	Data Rate	Nyquist Freq	Max IL @ Nyquist	Max IL @ 2x Nyquist
PCIe Gen3	8 GT/s	4 GHz	-20 dB	-35 dB
PCIe Gen4	16 GT/s	8 GHz	-24 dB	-36 dB
PCIe Gen5	32 GT/s	16 GHz	-28 dB	-40 dB
USB 3.1 Gen2	10 Gbps	5 GHz	-20 dB	-30 dB
10GBASE-KR	10.3125 Gbps	5.15 GHz	-22 dB	-35 dB
25GBASE-KR	25.78125 Gbps	12.89 GHz	-25 dB	-38 dB

Return Loss Requirements

Return loss (RL) measures the impedance matching quality at connectors, via transitions, and package interfaces. It is measured as S11 (input reflection) and S22 (output reflection). High return loss means good impedance match (low reflection), which is desirable.

Return Loss Definition

RL (dB) = -20 * log10( |Gamma| )
where Gamma = (Z_actual - Z_reference) / (Z_actual + Z_reference)

For Z_actual = 55 ohm, Z_ref = 50 ohm:
Gamma = (55-50)/(55+50) = 0.0476
RL = -20 * log10(0.0476) = 26.4 dB (PASS for most standards requiring > 15 dB)

Interactive S-Parameter Compliance Checker

IL @ Nyquist: -- dB | RL: -- dB | Result: Configure parameters

Impedance Profile Compliance

Beyond frequency-domain S-parameters, many standards also specify time-domain impedance requirements using TDR (Time Domain Reflectometry). The TDR impedance profile reveals discontinuities at specific physical locations (connectors, vias, package transitions).

Standard	Z_diff Target	Z Tolerance	TDR Rise Time	Test Method
PCIe Gen3/4	85 ohm diff	+/- 15%	50 ps	IEEE 370-compliant
PCIe Gen5	85 ohm diff	+/- 10%	35 ps	IEEE 370-compliant
USB 3.0/3.1	90 ohm diff	+/- 15%	75 ps	Per USB-IF spec
10GBASE-KR	100 ohm diff	+/- 10%	50 ps	IEEE 802.3 Clause 68
DDR4	80 ohm diff (DQ)	+/- 15%	100 ps	Per JEDEC
DDR5	80 ohm diff (DQ)	+/- 10%	50 ps	Per JEDEC

S-Parameter Measurement Best Practices

Accurate S-parameter measurements are critical for compliance verification. Common pitfalls include:

De-embedding errors: Test fixtures and launch structures must be accurately de-embedded using TRL (Thru-Reflect-Line) or 2x-Thru calibration methods. Poor de-embedding corrupts the measured channel response.
Port impedance mismatch: VNA (Vector Network Analyzer) calibration must match the DUT reference impedance. A 50 ohm VNA measuring a 100 ohm differential channel requires a balun or mathematical mode conversion.
Causality violations: Non-causal S-parameters (time-domain impulse response shows energy before the stimulus) indicate measurement or processing errors. Use causality enforcement algorithms.
Passivity violations: |S21|^2 + |S11|^2 should be <= 1 at all frequencies. Violations indicate noise or calibration errors.

IEEE 370 Standard

IEEE 370-2020 defines standardized methods for electrical characterization of interconnects up to 50 GHz. It specifies test fixture designs, calibration methods, and de-embedding procedures. Following IEEE 370 ensures consistent and reproducible S-parameter measurements across different labs and equipment.

Crosstalk Compliance (NEXT and FEXT)

Multi-lane SerDes systems must also meet crosstalk specifications. Near-End Crosstalk (NEXT) and Far-End Crosstalk (FEXT) are measured between adjacent lanes:

Crosstalk S-Parameters

NEXT = |S31| (coupling from port 1 to adjacent port 3 at same end)
FEXT = |S41| (coupling from port 1 to adjacent port 4 at far end)

For PCIe Gen5: FEXT < -25 dB at 16 GHz
For 25GBASE-KR: ICN (Integrated Crosstalk Noise) < -30 dB

2. Eye Mask Testing

What is an Eye Mask?

An eye mask (or eye template) defines a forbidden region within the eye diagram. If any signal trajectory enters this region, the device fails compliance testing. The mask is defined by a polygon (or set of polygons) in the voltage-time plane of the eye diagram, and its dimensions are specified per standard.

The eye mask typically consists of:

Inner mask (diamond/hexagon): The central keep-out region. The signal eye must be wider and taller than this shape.
Upper and lower boundary: Maximum allowed voltage excursion. Signal must not exceed VDD + overshoot limit or go below GND - undershoot limit.

Standard Eye Mask Definitions

Standard	Mask Shape	Min Eye Height	Min Eye Width (%UI)	Max Overshoot
PCIe Gen3 (8GT/s)	Hexagonal	175 mV	40%	+/- 300 mV
PCIe Gen4 (16GT/s)	Hexagonal	100 mV	30%	+/- 250 mV
USB 3.0 (5Gbps)	Diamond	200 mV	40%	Not specified
USB 3.1 Gen2	Diamond	100 mV	35%	+/- 150 mV
10GBASE-KR	Hexagonal	74 mV	28%	N/A (AC coupled)

Interactive Eye Mask Simulation

Mask Hits: 0 | Total Traces: 0 | Result: --

Eye Mask Testing Methodology

Eye mask testing follows a standardized procedure that ensures repeatable results across different test equipment and laboratories:

Pattern selection: Use the compliance pattern specified by the standard (e.g., PRBS-7 for USB 3.0, PRBS-31 for PCIe Gen4/5, Modified Compliance Pattern for USB 3.1).
Clock recovery: Enable golden PLL or reference clock recovery with the specified bandwidth and peaking (per standard). The CDR settings affect the eye width measurement.
Acquisition: Capture sufficient waveform data. Typically 10,000-100,000 UI are overlaid to construct the eye. Some standards specify a minimum acquisition time.
Mask placement: The mask is centered on the eye based on the recovered clock and the measured signal amplitude. Automatic mask alignment algorithms center vertically and horizontally.
Violation counting: Count the number of waveform samples that fall within the mask polygon. Zero violations = Pass. Some standards allow a small violation ratio (e.g., 5 hits per 10^6 samples).

CDR Bandwidth Affects Eye Width

The CDR (Clock Data Recovery) bandwidth used during eye mask testing directly affects the measured eye width. A wider CDR bandwidth tracks more low-frequency jitter, making the eye appear wider. A narrow CDR bandwidth lets more jitter through, closing the eye. Always use the exact CDR settings specified by the standard for compliance testing. Different CDR settings can change the measured eye width by 10-20%.

Equalizer Impact on Eye Mask Compliance

Many modern standards specify eye mask testing at a reference receiver that includes equalization. The measurement point after equalization is called the "equalized eye" and the mask dimensions are adjusted accordingly (typically smaller mask = tighter requirement but measured after EQ has opened the eye).

Standard	Measurement Point	Reference EQ	Mask After EQ
PCIe Gen3	TX output (no EQ)	None	175 mV / 40% UI
PCIe Gen4	After reference CTLE	CTLE: 8-12 dB peak	100 mV / 30% UI
PCIe Gen5	After reference CTLE+DFE	CTLE + 1-tap DFE	60 mV / 25% UI
USB 3.0	TX output (no EQ)	None	200 mV / 40% UI
USB 3.1 Gen2	TX output (no EQ)	None	100 mV / 35% UI

Automated Eye Mask Testing

Modern oscilloscopes include built-in eye mask testing capabilities. The workflow for automated testing:

Select the standard from the scope's compliance test library
Connect the DUT output to the scope through the specified test fixture
The scope automatically acquires the pattern, recovers the clock, aligns the mask, and reports pass/fail with margin
Eye height margin and eye width margin are reported as the distance from the closest waveform point to the mask boundary
Some tools report "mask margin" as a percentage: how much the mask could be enlarged before the first violation occurs

3. Jitter Compliance

Jitter Taxonomy

Jitter is the deviation of a signal's transition time from its ideal position. Understanding the jitter taxonomy is essential for compliance testing because different jitter components have different root causes and statistical behaviors.

Jitter Type	Abbreviation	Nature	Root Cause	Distribution
Total Jitter	TJ	Combined	All sources	Convolution of all
Random Jitter	RJ	Unbounded	Thermal noise, shot noise	Gaussian
Deterministic Jitter	DJ	Bounded	Systematic sources	Bounded peak-peak
Data-Dependent Jitter	DDJ	Deterministic	ISI, duty cycle distortion	Pattern-dependent
Periodic Jitter	PJ	Deterministic	Crosstalk, EMI, PLL spurs	Sinusoidal/periodic
Bounded Uncorrelated Jitter	BUJ	Deterministic	Crosstalk, supply noise	Bounded

Total Jitter Decomposition (at a given BER)

TJ(BER) = DJ_pp + 2 * N(BER) * RJ_rms

Where N(BER) is the Q-factor:
BER = 10^-12 --> N = 14.07 (standard compliance target)
BER = 10^-15 --> N = 15.88

Example: DJ = 25 ps, RJ_rms = 1.5 ps
TJ(10^-12) = 25 + 2 * 14.07 * 1.5 = 67.2 ps

Jitter Budget Per Standard

Standard	UI (ps)	Max TJ @ BER=10^-12	Max DJ	Max RJ_rms
PCIe Gen3	125	73 ps (0.58 UI)	35 ps	1.5 ps
PCIe Gen4	62.5	36 ps (0.58 UI)	17 ps	0.75 ps
PCIe Gen5	31.25	18 ps (0.58 UI)	8 ps	0.38 ps
USB 3.0	200	100 ps (0.50 UI)	50 ps	3.0 ps
10GBASE-KR	97.1	55 ps (0.57 UI)	25 ps	1.2 ps

Interactive Jitter Measurement Simulation

TJ: -- ps | DJ_pp: -- ps | RJ contribution: -- ps | Budget Status: --

Jitter Separation Techniques

Accurate jitter separation is essential for identifying root causes and allocating budget. The measurement techniques include:

Technique	What It Separates	Equipment	Accuracy
Dual-Dirac Model	RJ from DJ (TJ decomposition)	Real-time or sampling scope	Good for > 10^4 UI
Tail-Fit Algorithm	RJ from DJ using histogram tails	Sampling scope with software	Excellent with 10^6+ UI
Spectral Analysis	PJ from DDJ and BUJ	Sampling scope with FFT	Good for periodic sources
Pattern-Based (Q-scale)	DDJ from total DJ	BER tester or Q-scale software	Excellent for DDJ identification
Phase Noise Integration	RJ_rms from clock source	Signal source analyzer or spectrum analyzer	Very high for clock jitter

Jitter Transfer and Jitter Peaking

The CDR (Clock Data Recovery) circuit in a receiver has a jitter transfer function that determines how input jitter appears at the recovered clock output. The transfer function has a low-pass characteristic with bandwidth equal to the CDR loop bandwidth.

CDR Jitter Transfer (2nd order PLL)

H(s) = (2*zeta*omega_n*s + omega_n^2) / (s^2 + 2*zeta*omega_n*s + omega_n^2)

Where:
omega_n = natural frequency of the CDR loop
zeta = damping factor (typically 0.7-1.0)

Jitter peaking = 20*log10( |H(j*omega)| )_max
For zeta = 0.7: Peaking = ~2.3 dB at omega ~ omega_n
For zeta = 1.0: Peaking = 0 dB (critically damped, no peaking)

Jitter Peaking Cascading Problem

When multiple CDRs are cascaded (e.g., switch -> cable -> retimer -> cable -> receiver), each CDR's jitter peaking multiplies. If each CDR has 2 dB of peaking, three cascaded CDRs can create 6 dB of jitter amplification at frequencies near the CDR bandwidth. Standards like PCIe and Ethernet specify maximum jitter transfer and jitter peaking limits to prevent this cascading problem.

Real-Time vs Equivalent-Time Jitter Measurement

REAL-TIME OSCILLOSCOPE

Pros: Captures every single bit, can see rare events, supports pattern triggering
Cons: Limited bandwidth (typically 16-70 GHz), higher noise floor
Best for: TJ/DJ/RJ separation, pattern-dependent jitter, eye mask testing
Required for: PCIe Gen4/5 TX compliance, USB TX compliance

EQUIVALENT-TIME (SAMPLING) OSCILLOSCOPE

Pros: Very high bandwidth (70-110 GHz), low noise floor
Cons: Misses rare events, requires repetitive signal, slower acquisition
Best for: High-precision jitter histograms, bathtub curves, TDR/TDT
Required for: 56+ Gbps PAM4 measurements, high-precision return loss

4. BER Concepts

Bit Error Rate Fundamentals

Bit Error Rate (BER) is the probability that a received bit is incorrect. For high-speed serial links, the target BER is typically 10^-12 (one error per trillion bits) or better. At multi-gigabit data rates, even this seemingly small error rate can cause significant issues without forward error correction (FEC).

BER and Measurement Time

Bits to transmit for statistical confidence at BER = 10^-12:
N_bits >= 10 / BER_target = 10^13 bits

At 10 Gbps: Time = 10^13 / 10^10 = 1000 seconds (~17 minutes)
At 25 Gbps: Time = 10^13 / 25^10 = 400 seconds (~7 minutes)
At 32 GT/s (PCIe Gen5): Time = 10^13 / 32*10^9 = 312 seconds (~5 minutes)

Bathtub Curves

A bathtub curve plots BER as a function of sampling point within a Unit Interval (UI). As the sampling point moves from the center of the eye toward the edges, the BER increases. The curve resembles a bathtub shape, with very low BER in the center and steep walls at the edges.

The bathtub curve is constructed by integrating the jitter probability density function. The width of the "flat bottom" (where BER is below the target) defines the usable timing margin.

Interactive BER Calculator and Bathtub Curve

UI: -- ps | Timing Margin @ BER=10^-12: -- ps (-- UI) | Status: --

BER Extrapolation

In practice, measuring BER directly at 10^-12 takes many minutes. Instead, the bathtub curve is measured at higher BER levels (10^-6 to 10^-9) and extrapolated to 10^-12 using the dual-Dirac jitter model. This separation of RJ and DJ components enables accurate extrapolation in seconds rather than minutes.

Dual-Dirac Jitter Model for BER Extrapolation

The dual-Dirac model is the industry-standard approach for separating random jitter (RJ) from deterministic jitter (DJ) using BER measurements. It models the jitter PDF as the sum of two Gaussian distributions separated by the deterministic jitter component:

Dual-Dirac BER Model

BER(t) = 0.5 * erfc((t - mu_L) / (sqrt(2) * sigma_RJ)) + 0.5 * erfc((mu_R - t) / (sqrt(2) * sigma_RJ))

Where:
mu_L, mu_R = Left and right mean positions (DJ_pp = mu_R - mu_L)
sigma_RJ = RMS random jitter
erfc() = Complementary error function

BER floor occurs when: DJ_pp > 0.5 UI (dual-Dirac peaks overlap)

BER Floor -- The Compliance Killer

When deterministic jitter is large enough that the two Gaussian tails overlap significantly, the bathtub curve develops a "floor" -- a minimum BER that cannot be improved by any amount of timing adjustment. If the BER floor is above the target BER (e.g., floor at 10^-9 with a target of 10^-12), no sampling point will meet the spec. The only fix is to reduce DJ by improving the channel (less ISI), reducing crosstalk, or applying equalization.

Practical BER Measurement Equipment

Instrument	BER Measurement Method	Speed Range	Key Advantage
BERT (Bit Error Rate Tester)	Direct bit comparison (TX known pattern, RX compare)	100 Mbps - 64 Gbps	Most accurate; true BER measurement
Sampling Oscilloscope	Jitter histogram + dual-Dirac extrapolation	DC - 80 GHz bandwidth	Gives bathtub curve + jitter decomposition
Real-time Oscilloscope	Software BER from captured waveform	DC - 70 GHz bandwidth	Captures rare events; pattern-dependent analysis
Built-in PRBS Checker	IC-internal error counter	Device-specific	No external equipment; measures post-EQ BER

PRBS Pattern Selection for BER Testing

The pseudo-random bit sequence (PRBS) pattern length affects the types of ISI captured. PRBS-7 (127 bits) is too short for most SerDes testing. PRBS-15 (32767 bits) is commonly used for NRZ compliance. PRBS-23 (8.4M bits) exercises longer ISI tails. PRBS-31 (2.1G bits) is required for some 25G+ standards to stress the CDR tracking bandwidth. Longer patterns create more low-frequency content, which stresses AC coupling and baseline wander.

Forward Error Correction (FEC)

For newer standards operating at extreme data rates, Forward Error Correction relaxes the raw BER requirement to a pre-FEC BER (typically 10^-6 to 10^-4), while the coded BER after FEC correction meets the application requirement (10^-12 or better).

Standard	FEC Type	Pre-FEC BER Target	Post-FEC BER	Coding Overhead
PCIe Gen3/4	None	N/A	10^-12 (raw)	128b/130b (~1.5%)
PCIe Gen5 (optional)	None/FLIT	N/A	10^-12 (raw)	128b/130b + CRC
PCIe Gen6	CRC + retry	10^-6	10^-12 effective	PAM4, 1b/1b FLIT
Ethernet 25G	RS-FEC (528,514)	2.4e-4	10^-13	~2.7%
Ethernet 100G (KP4)	RS-FEC (544,514)	2.4e-4	10^-15	~5.8%
Ethernet 400G	RS-FEC (544,514)	2.4e-4	10^-15	~5.8%

FEC and Channel Compliance

When FEC is used, the channel compliance requirements change. The insertion loss budget can be more relaxed because the system tolerates a higher raw BER. However, the BER must still be below the FEC threshold -- if raw BER exceeds the FEC correction capability, the link fails catastrophically (error floor). This is why compliance testing with FEC-based standards measures both raw BER and corrected BER.

Statistical vs Time-Domain BER Analysis

There are two fundamental approaches to predicting BER in channel simulation:

STATISTICAL ANALYSIS

Method: Convolves the channel impulse response with all possible bit patterns to compute the exact probability distribution at the sampling point.
Speed: Seconds to minutes
Accuracy: Exact for linear systems, approximate for DFE
Limitation: Cannot model non-linear effects like CDR tracking or DFE error propagation
Use: Initial design space exploration, COM calculation

TIME-DOMAIN (BIT-BY-BIT)

Method: Simulates every bit through the channel and EQ. Captures all non-linear effects.
Speed: Hours to days for 10^12 bits
Accuracy: Exact (given sufficient simulation length)
Limitation: Impractical to simulate enough bits for direct 10^-12 BER
Use: Final verification, AMI GetWave analysis, DFE validation

5. Receiver Margining

JTOL (Jitter Tolerance) Testing

Jitter tolerance testing measures how much jitter a receiver can withstand while maintaining a target BER. It is the inverse of jitter generation testing: instead of measuring what the transmitter produces, we test what the receiver can accept.

A JTOL curve plots the maximum tolerable sinusoidal jitter (SJ) amplitude versus SJ frequency. The resulting curve typically has three regions:

Low frequency: High tolerance (CDR tracks the jitter)
Corner frequency: CDR bandwidth transition region
High frequency: Lower tolerance (CDR cannot track, eye closes)

Stressed Eye Testing

A stressed eye is an intentionally degraded eye pattern applied to the receiver during compliance testing. It simulates worst-case channel conditions. The stressed eye is calibrated to specific dimensions (height, width, jitter) at a reference receiver, then the DUT receiver must successfully recover data from this degraded signal.

Interactive Stressed Eye Simulation

Eye Height: -- mV | Eye Width: -- UI | Status: Adjust stress parameters

Receiver Sensitivity Testing

Receiver sensitivity defines the minimum signal amplitude a receiver can detect while maintaining the target BER. This is tested by gradually reducing the input signal amplitude until errors appear.

Standard	Min RX Sensitivity (Vdiff pp)	Test Method
PCIe Gen3	175 mV	Stressed eye with calibrated SJ+RJ
PCIe Gen4	100 mV	Stressed eye with calibrated SJ+RJ+ISI
PCIe Gen5	60 mV (post-EQ)	Stressed eye + reference EQ
USB 3.0	200 mV	LFPS detect + compliance pattern
USB 3.1 Gen2	120 mV	Compliance pattern at min amplitude
10GBASE-KR	74 mV (post-EQ)	IEEE 802.3 stressed receiver test

Link Margin Assessment

The total link margin is the difference between the available signal quality and the minimum required. It accounts for all degradation mechanisms:

Link Margin Budget

Margin (dB) = TX_amplitude - IL_channel - IL_connector - XTALK_penalty - RJ_penalty - ISI_residual - RX_sensitivity

Example (PCIe Gen4):
TX output = 1000 mV (0 dBm)
Channel IL @ 8 GHz = -18 dB (126 mV delivered)
Connector loss = -2 dB (100 mV)
XTALK = -1 dB (89 mV)
RJ penalty = -1 dB (79 mV)
RX sensitivity = 100 mV
Margin = 79 mV / 100 mV = -2 dB (FAIL - needs EQ)

With CTLE + DFE:
EQ gain = +12 dB at Nyquist
Effective signal = 79 mV * 4 = 316 mV
Margin = 316 / 100 = 10 dB (PASS)

JTOL Curve Characteristics

The jitter tolerance curve reveals the CDR (Clock Data Recovery) bandwidth and the receiver's overall jitter handling capability. Key features:

Flat region (low freq): CDR fully tracks the applied jitter. Tolerance equals the entire UI (limited only by CDR range).
CDR bandwidth corner (f_n): The CDR loop bandwidth, typically 1-10 MHz. Above this frequency, tolerance drops.
Rolloff region: Tolerance decreases at -20 dB/decade (first-order CDR) or -40 dB/decade (second-order CDR).
High-frequency floor: At high SJ frequencies, tolerance reaches a minimum set by the residual timing margin within the eye.

PCIe Gen5 JTOL Challenge

With only 31.25 ps UI, the high-frequency jitter tolerance floor for PCIe Gen5 is extremely tight (< 0.1 UI = 3.1 ps). This requires extremely low-jitter CDR designs with PLL bandwidths optimized for the specific channel loss profile. CDR bandwidth that is too wide amplifies high-frequency noise; too narrow misses low-frequency jitter tracking.

6. Protocol-Specific Compliance Labs

6.1 DDR4 / DDR5 Compliance

DDR memory interfaces use source-synchronous parallel signaling with tight timing margin requirements. Unlike SerDes links, DDR relies on a strobe signal (DQS) for clock recovery at the byte level.

Parameter	DDR4-3200	DDR5-4800	DDR5-6400
Data Rate	3200 MT/s	4800 MT/s	6400 MT/s
VDDQ	1.2V	1.1V	1.1V
Signaling	POD (Pseudo Open Drain)	POD	POD
Impedance (ZQ)	240 ohm	240 ohm	240 ohm
Setup Time (tDS)	45 ps	30 ps	20 ps
Hold Time (tDH)	45 ps	30 ps	20 ps
Write Leveling	Yes	Yes	Yes
Read DQS Preamble	1-2 tCK	2-4 tCK	2-4 tCK

DDR5 Key Changes from DDR4

DDR5 introduces decision feedback equalization (DFE) at the memory controller, on-die ECC, and a new training sequence. The channel length budget is shorter due to higher data rates, making PCB routing and SI simulation even more critical.

DDR Timing Margin Calculator

DDR Standard:

Measured Setup (ps):

Measured Hold (ps):

Setup Margin

--

Hold Margin

--

Verdict

--

6.2 USB 3.0 / 3.1 Compliance

USB SuperSpeed uses a SerDes architecture with embedded clocking, 8b/10b (USB 3.0) or 128b/132b (USB 3.1 Gen2) encoding, and a compliance mode that exercises all data patterns for testing.

Parameter	USB 3.0 (Gen1)	USB 3.1 Gen2	USB 3.2 Gen2x2
Data Rate	5 Gbps	10 Gbps	2 x 10 Gbps
Encoding	8b/10b	128b/132b	128b/132b
TX Amplitude (Vdiff pp)	0.9-1.3V	0.9-1.3V	0.9-1.3V
TX De-emphasis	-3.5 dB	-3.5 dB / -6 dB	-3.5 dB / -6 dB
Max TJ (TX)	100 ps	50 ps	50 ps
RX Sensitivity	200 mV diff	120 mV diff	120 mV diff

TX COMPLIANCE PASS

Amplitude: 1.05V (within 0.9-1.3V)
De-emphasis: -3.3 dB (within -3.5 +/- 1 dB)
Rise time: 75 ps (within 50-120 ps)
TJ: 38 ps (< 50 ps limit)

TX COMPLIANCE FAIL

Amplitude: 0.82V (below 0.9V minimum)
De-emphasis: -7.2 dB (exceeds -6 dB max)
Rise time: 130 ps (exceeds 120 ps max)
TJ: 62 ps (exceeds 50 ps limit)

6.3 PCIe Gen3 / Gen4 / Gen5 Compliance

PCI Express uses NRZ signaling with progressively tighter budgets across generations. PCIe Gen5 (32 GT/s) pushes NRZ to its practical limits, requiring sophisticated equalization at both TX and RX.

Parameter	PCIe Gen3	PCIe Gen4	PCIe Gen5
Data Rate	8 GT/s	16 GT/s	32 GT/s
UI (ps)	125	62.5	31.25
Encoding	128b/130b	128b/130b	128b/130b
TX Vdiff pp	0.8-1.2V	0.8-1.2V	0.8-1.2V
TX De-emphasis Presets	P0-P10	P0-P10	P0-P10
TX Pre-shoot	N/A	Up to 2.5 dB	Up to 4.5 dB
RX CTLE	Required	Required	Required
RX DFE	Optional	1+ taps	4+ taps

PCIe Gen5 Challenge

At 32 GT/s, the UI is only 31.25 ps. Channel loss budgets are extremely tight, and the equalization must recover more than 20 dB of insertion loss at Nyquist. Most designs require careful via optimization, low-loss materials (Dk < 3.5, Df < 0.005), and validated AMI models for compliance verification.

6.4 Ethernet 10GBASE-KR Compliance

10GBASE-KR is the backplane Ethernet standard for 10 Gbps links over PCB traces (no cable). It defines stringent channel requirements and mandates link training with adaptive equalization.

Parameter	Specification
Data Rate	10.3125 Gbps (64b/66b encoded)
Max Channel Loss @ 5.15 GHz	-22 dB
TX Amplitude	750 mV - 1200 mV (differential peak)
TX Equalization	3-tap FIR (pre, main, post)
RX Equalization	CTLE + DFE (auto-negotiated)
Link Training	IEEE 802.3 Clause 72
BER Target	10^-12

Protocol Compliance Testing Equipment

Each protocol has specific test equipment requirements and authorized test suites. Understanding the test setup is essential for efficient compliance verification:

Protocol	Compliance Body	Required Equipment	Key Tests
PCIe	PCI-SIG	Real-time scope (> 16 GHz BW for Gen5), ISI channel, SigTest software	TX compliance, RX JTOL, link training
USB 3.x	USB-IF	Real-time scope (> 6 GHz), SigTest/USB-IF compliance suite, fixture boards	TX eye mask, RX sensitivity, LFPS
DDR4/5	JEDEC	Scope with DDR decode, BER tester, SI simulation tool	Timing margins (setup/hold), eye height, impedance
Ethernet	IEEE	BER tester, programmable SJ source, PRBS generator	TX output, RX JTOL, BER at stressed eye

Compliance Test Workflow

A typical SerDes compliance verification follows this workflow:

Pre-silicon (simulation): Run channel simulation with IBIS-AMI models and S-parameters of the channel. Verify COM > 3 dB, eye height/width meet mask, jitter budget allocation.
Post-silicon (lab measurement): Build test boards with calibrated fixtures. Measure TX parameters with real-time oscilloscope. Measure RX BER/JTOL with BER tester.
System-level: Test complete product (PCB + connectors + cables) under operating conditions. Verify link stability, error rates, and margin over temperature.
Certification: Submit to compliance body (PCI-SIG, USB-IF, etc.) for official testing and logo authorization.

Common Compliance Failure Root Causes

Design Issue

Top 5 SerDes Compliance Failure Root Causes

1. TX Emphasis Misconfiguration

Wrong de-emphasis preset selected during link training. The TX equalization does not match the channel loss. Solution: Verify TX preset table in firmware/driver matches the spec.

2. Via Stub Resonance

Non-back-drilled vias create stubs that resonate within the signal bandwidth, causing notch in S21. Solution: Back-drill all high-speed vias, or use blind/buried vias.

3. Impedance Discontinuity at Connector

Poor connector breakout routing causes impedance mismatch exceeding 15%. Solution: Use 3D EM simulation to optimize breakout, add compensation pads.

4. Insufficient RX Equalization

RX CTLE and DFE settings not adapting properly due to firmware bug or insufficient training time. Solution: Extend link training duration, verify adaptation convergence.

Pre-Compliance Testing Saves Time and Money

Official compliance testing costs $5,000-$50,000 per attempt depending on the protocol. Performing thorough pre-compliance testing in your own lab (with the same test procedures and equipment as the official test) dramatically reduces the risk of failure. Invest in proper test fixtures and understand the test methodology before submitting for official certification.

7. Knowledge Check - SerDes Compliance

Q1: What S-parameter measures channel insertion loss?

S11 (input reflection coefficient) S21 (forward transmission coefficient) S22 (output reflection coefficient) S12 (reverse transmission coefficient)

S21 measures the forward transmission from port 1 to port 2, which represents the channel insertion loss. S11 and S22 measure return loss (reflections) at each port.

Q2: In an eye mask test, what does a "mask hit" indicate?

The signal has exceeded the supply voltage The clock has recovered successfully A signal trace has entered the forbidden region of the eye mask The signal amplitude meets the minimum requirement

A mask hit means the signal waveform has crossed into the keep-out zone defined by the eye mask polygon. Any mask hit constitutes a compliance failure.

Q3: What is the relationship between Total Jitter (TJ), Random Jitter (RJ), and Deterministic Jitter (DJ)?

TJ = RJ + DJ (simple addition) TJ = DJ_pp + 2 * N(BER) * RJ_rms (DJ is bounded, RJ is extrapolated) TJ = sqrt(RJ^2 + DJ^2) (RSS addition) TJ = max(RJ, DJ) (worst case)

DJ is bounded and added peak-to-peak. RJ is Gaussian (unbounded) and its contribution depends on the target BER through the N(BER) multiplier. At BER=10^-12, N=14.07, so RJ_rms is multiplied by ~28.

Q4: What does a bathtub curve plot?

Signal amplitude vs frequency Impedance vs trace length BER vs sampling point within a Unit Interval Insertion loss vs return loss

A bathtub curve shows how BER varies as the sampling point moves across the UI. The center of the eye has the lowest BER, and BER increases steeply toward the edges, creating the characteristic bathtub shape.

Q5: Which DDR5 feature is new compared to DDR4?

Write leveling Decision Feedback Equalization (DFE) at the controller On-die termination (ODT) DQS strobe signaling

DDR5 introduces DFE at the memory controller to handle the increased ISI at higher data rates (4800+ MT/s). Write leveling, ODT, and DQS were already present in DDR4.

Q6: What de-emphasis level does PCIe Gen4 use at TX preset P3 for long channels?

0 dB (no de-emphasis) -2.5 dB -3.5 dB (standard de-emphasis) -6 dB (maximum)

PCIe Gen3/Gen4 TX presets define various de-emphasis levels. P3 is a common starting point with -3.5 dB de-emphasis. The link training protocol negotiates the optimal preset based on channel characteristics.

Q7: Why is BER extrapolation from bathtub curves preferred over direct BER measurement at 10^-12?

Direct measurement requires collecting 10^13 bits which takes many minutes; extrapolation is much faster Direct measurement is less accurate than extrapolation Extrapolation requires simpler test equipment Direct measurement cannot distinguish RJ from DJ

To statistically confirm BER=10^-12, you need approximately 10^13 bits. At 10 Gbps, that is ~17 minutes per sampling point. A bathtub curve requires many sampling points. Extrapolation measures at higher BER levels (10^-6 to 10^-9) and uses the dual-Dirac model to predict 10^-12 performance in seconds.

Q8: For USB 3.1 Gen2 TX compliance, what is the required differential output amplitude range?

400-800 mV differential peak-to-peak 900-1300 mV differential peak-to-peak 1500-2000 mV differential peak-to-peak 200-400 mV differential peak-to-peak

USB 3.0 and USB 3.1 Gen2 both specify 0.9V to 1.3V (900-1300 mV) differential peak-to-peak amplitude at the TX output. Below 900 mV the receiver may not detect the signal; above 1300 mV the signal may cause EMI issues.

Additional Resources for Compliance Testing

Resource	Description	Availability
PCI-SIG CEM Spec	Card Electromechanical specification with TX/RX compliance test procedures	PCI-SIG members
USB-IF Compliance Program	Complete USB compliance test specifications and authorized test labs	USB-IF website
IEEE 802.3 Clause 68-72	Electrical compliance test procedures for Ethernet	IEEE Standards
JEDEC JESD79-4/5	DDR4/DDR5 specification with timing and SI requirements	JEDEC members
IEEE 370-2020	Standardized methods for electrical characterization of interconnects	IEEE Standards
OIF CEI standards	Common Electrical Interface for backplane and chip-to-chip links	OIF website

Compliance Testing Best Practice Summary

1) Start compliance analysis during the schematic/layout design phase using simulation. 2) Build test coupons and measure S-parameters before committing to full board fabrication. 3) Perform pre-compliance testing in your lab using the exact procedures from the standard. 4) Document all measurement setups and results for correlation with official testing. 5) Budget 2-3 board spins for high-speed designs. 6) Maintain close communication with your IC vendor's applications engineers for IBIS-AMI model support and equalization guidance.