Common Impedance Targets
Standard impedance requirements for common high-speed interfaces. Always verify against the latest specification revision.
| Interface | Type | Impedance Target | Tolerance | Notes |
|---|---|---|---|---|
| USB 2.0 | Differential | 90 Ω | ±10% | 480 Mbps max; referenced to GND plane |
| USB 3.x / USB4 | Differential | 85 Ω | ±10% | 5–40 Gbps; tightly coupled pairs, low-loss material recommended for USB4 |
| PCIe Gen 3/4/5 | Differential | 85 Ω | ±10% | 8–32 GT/s; controlled impedance vias required for Gen 4+ |
| PCIe Gen 6 | Differential | 85 Ω | ±5% | 64 GT/s PAM4; ultra-low-loss materials, strict impedance control |
| DDR4 Data / DQS | Single-ended | 40 Ω | ±10% | On-die termination (ODT); fly-by topology for clock/address |
| DDR5 Data / DQS | Single-ended | 40 Ω | ±10% | Decision feedback equalization (DFE) in receiver; point-to-point topology |
| DDR4/5 Clock/Address | Single-ended | 40 Ω | ±10% | DDR4: fly-by daisy-chain; DDR5: point-to-point per channel |
| HDMI 2.1 | Differential | 100 Ω | ±10% | Up to 48 Gbps; FRL encoding; AC-coupled |
| DisplayPort 2.0 | Differential | 100 Ω | ±10% | Up to 80 Gbps aggregate; UHBR modes |
| Ethernet 10GBASE-KR | Differential | 100 Ω | ±10% | Backplane; requires equalization at receiver |
| SATA III | Differential | 100 Ω | ±10% | 6 Gbps; AC-coupled; legacy interface |
| MIPI D-PHY | Differential | 100 Ω | ±10% | Camera and display interface; up to 4.5 Gbps per lane |
| MIPI M-PHY | Differential | 50 Ω / 100 Ω | ±10% | UFS and UniPro; single-ended 50 Ω or differential 100 Ω |
| SPI / I2C / UART | Single-ended | 50 Ω (if controlled) | — | Generally not impedance-controlled unless trace length exceeds Lcrit |
Dielectric Materials Comparison
Properties of common PCB laminate materials. Dk and Df values are approximate and vary with frequency and resin content.
| Material | Manufacturer | Dk (@ 10 GHz) | Df (@ 10 GHz) | Tg (°C) | Typical Applications |
|---|---|---|---|---|---|
| Standard FR-4 (Tg 135) | Various | 4.2–4.5 | 0.020–0.025 | 135 | Low-speed consumer electronics, cost-sensitive designs |
| High-Tg FR-4 | Various | 4.2–4.5 | 0.018–0.022 | 170–180 | Lead-free assembly, moderate speed designs up to 5 Gbps |
| Megtron 4 (R-5775) | Panasonic | 3.8 | 0.008 | 200 | Servers, networking, 10–16 Gbps links |
| Megtron 6 (R-5775K) | Panasonic | 3.4 | 0.004 | 200 | Data center, 25–56 Gbps NRZ/PAM4 |
| Megtron 7 (R-5785) | Panasonic | 3.2 | 0.002 | 200 | Ultra-high-speed 112 Gbps PAM4, next-gen data center |
| Isola IS680 AG | Isola | 3.6 | 0.007 | 200 | Mid-range high-speed, automotive radar substrates |
| Isola I-Speed | Isola | 3.6 | 0.009 | 200 | High-speed digital, 10G Ethernet, PCIe Gen 3/4 |
| Isola Astra MT77 | Isola | 3.0 | 0.0017 | 200 | mmWave, 5G base stations, 77 GHz automotive radar |
| Rogers RO4003C | Rogers | 3.38 | 0.0027 | 280+ | RF/microwave, antennas, low-loss high-frequency circuits |
| Rogers RO4350B | Rogers | 3.48 | 0.0037 | 280+ | RF hybrid boards, can be processed with standard FR-4 methods |
| Rogers RO3003 | Rogers | 3.00 | 0.0013 | — | PTFE-based, mmWave, satellite communications |
| Nelco N4000-13 EP SI | Park/Nelco | 3.7 | 0.008 | 210 | High-speed backplanes, network switches |
Common EMI Limits Summary
Summary of radiated emission limits for FCC and CISPR Class B. All radiated values at 3 m measurement distance.
| Frequency Range | FCC Class B (dBμV/m @ 3 m) | CISPR 32 Class B (dBμV/m @ 3 m) | EN 55032 Class B (dBμV/m @ 3 m) |
|---|---|---|---|
| 30–88 MHz | 40.0 | 40.0 | 40.0 |
| 88–230 MHz | 43.5 | 47.0 | 47.0 |
| 230–960 MHz | 46.0 | 47.0 | 47.0 |
| 960 MHz–6 GHz | 54.0 | 47.0–57.0 | 47.0–57.0 |
Limits vary by region. Always reference the specific standard revision applicable to your target market. Conducted emission limits (150 kHz–30 MHz) apply separately and must also be met. Quasi-peak (QP) and average detectors each have distinct limits.
Copper Weight & Trace Parameters
Standard copper foil weights with corresponding thickness values and typical current-carrying capacity. Current values are approximate for outer-layer traces at 10°C rise per IPC-2221.
| Copper Weight (oz) | Thickness (mil) | Thickness (μm) | Max Current (1 oz width, 10°C rise) | Typical Use |
|---|---|---|---|---|
| 0.5 oz | 0.7 | 17.5 | ~0.7 A | Fine-pitch signal layers, HDI inner layers |
| 1 oz | 1.4 | 35 | ~1.0 A | Standard signal and power routing |
| 2 oz | 2.8 | 70 | ~1.8 A | Power planes, medium-current traces |
| 3 oz | 4.2 | 105 | ~2.5 A | High-current power distribution |
| 4 oz | 5.6 | 140 | ~3.2 A | Heavy power, bus bars, motor drives |
Current capacity values assume a 10 mil wide outer-layer trace with 10°C temperature rise above ambient. Inner layers carry approximately half the current of outer layers for the same geometry. Always verify with IPC-2152 charts or thermal simulation for production designs.
Via Parameters Reference
Common via types with typical drill sizes, pad dimensions, and design considerations for high-speed and high-density applications.
| Via Type | Drill Size (mil) | Pad Size (mil) | Aspect Ratio | Impedance Impact | Notes |
|---|---|---|---|---|---|
| Standard through-hole | 10–12 | 20–24 | 6:1–10:1 | Moderate — stub resonance concern | Most common; back-drill for >10 Gbps to remove stub |
| Micro via (laser) | 4–6 | 8–12 | 0.75:1–1:1 | Low — minimal parasitic L and C | Spans 1–2 layers; stacked or staggered for HDI |
| Buried via | 8–10 | 18–22 | 8:1–12:1 | Low — no surface stub | Connects inner layers only; requires sequential lamination |
| Blind via | 8–10 | 18–22 | 1:1 (laser) to 8:1 | Low-to-moderate | Starts at surface, ends on inner layer; saves routing space |
| Via-in-pad | 8–10 | BGA pad size | Varies | Moderate — improved vs. dog-bone | Filled & capped (VIPPO); required for ≤0.65 mm pitch BGA |
Via Inductance Formula
Lvia ≈ 5.08h [ln(4h/d) + 1] nH
where h = via height in mm, d = drill diameter in mm. A standard through-hole via (h = 1.6 mm, d = 0.3 mm) has approximately 0.9 nH of inductance. Use multiple vias in parallel (Ltotal ≈ L/N) to reduce inductance for power connections.
Common Connector Specifications
Key electrical and mechanical parameters for widely used board-level and cable connectors in high-speed digital and RF designs.
| Connector | Impedance | Max Data Rate | Mating Cycles | Key Specs |
|---|---|---|---|---|
| USB Type-C | 85 Ω diff | 80 Gbps (USB4) | 10,000 | 24-pin reversible; supports USB PD up to 240 W; SuperSpeed & DisplayPort Alt Mode |
| PCIe CEM (x16) | 85 Ω diff | 64 GT/s (Gen 6) | 500 | 164 pins (x16); card edge connector; requires controlled-impedance motherboard fingers |
| DDR5 DIMM | 40 Ω SE | 6400 MT/s | 400 | 288 pins; two 32-bit sub-channels; on-DIMM voltage regulator (PMIC) |
| SFP28 / QSFP28 | 100 Ω diff | 28 Gbps/lane | 250 | SFP28: 1 lane (25GbE); QSFP28: 4 lanes (100GbE); cage and heat sink required |
| M.2 (Key M) | 85 Ω diff | 32 GT/s (PCIe Gen 5) | 60 | 75-pin edge connector; supports NVMe x4; 2242/2260/2280 form factors |
| HDMI Type A | 100 Ω diff | 48 Gbps | 10,000 | 19 pins; HDMI 2.1 FRL mode; requires ESD protection and common-mode filtering |
| RJ45 (10GbE) | 100 Ω diff | 10 Gbps | 750 | 8P8C modular; Cat 6A shielded; integrated magnetics and PoE support common |
| SMA | 50 Ω SE | 18 GHz (standard) | 500 | Thread-on coupling; 2.92 mm variant extends to 40 GHz; used for test and RF I/O |
Data rates represent maximum specification capability and may require premium connector variants, low-loss PCB materials, and optimized via transitions to achieve. Mating cycle ratings assume proper alignment and insertion force. Consult manufacturer datasheets for detailed mechanical and electrical specifications.