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PCB Layout Review Checklist
Comprehensive layout review covering stackup, routing, planes, and manufacturing considerations.
Progress: 0 / 20 items
- Stackup verified against impedance targets and fabricator capability
- Impedance-controlled traces identified and width/spacing confirmed with field solver
- Decoupling capacitors placed within 2 mm of IC power pins with short via connections
- Return current paths are continuous and uninterrupted for all high-speed signals
- Differential pairs routed with consistent spacing and length-matched within spec
- Via usage reviewed: blind/buried vias for HDI, back-drill for high-speed stubs
- Ground plane integrity verified — no splits under high-speed signal routes
- Signal layer changes include return-path stitching vias near the transition
- Power plane shapes verified for adequate copper coverage and current capacity
- Thermal relief patterns appropriate for power and ground connections
- Mounting holes, connectors, and mechanical keep-outs match enclosure design
- Fiducial marks placed for SMT assembly (minimum 3, asymmetric pattern)
- Silkscreen text does not overlap pads, vias, or other silkscreen elements
- Board outline and panelization reviewed with PCB fabricator
- Minimum annular ring, trace/space, and drill size meet fabricator DFM rules
- Test points accessible for critical power rails, clocks, and debug signals
- No isolated copper islands (floating copper) on any layer
- ESD protection components placed close to connector pins with short traces
- Crystal/oscillator placement reviewed: short traces, guard ring, no routing underneath
- Design rule check (DRC) and electrical rule check (ERC) passing with no violations
Tip: Run DRC/ERC as the final gate before generating manufacturing outputs. Address every warning — suppressed violations have a habit of becoming field failures.
Signal Integrity Design Checklist
Key verification items for high-speed signal integrity on the PCB.
Progress: 0 / 15 items
- All high-speed nets identified and impedance requirements documented
- Trace impedance verified with 2D field solver for each layer in the stackup
- Critical length analysis performed — traces beyond Lcrit are impedance-controlled
- Termination strategy defined for each interface (series, parallel, AC, or on-die)
- Crosstalk analysis completed; 3W rule applied or spacing verified with simulation
- Length matching within specified tolerance for differential pairs and bus groups
- No stubs longer than 200 mils on high-speed nets (or back-drill planned)
- Reference plane transitions minimized; stitching capacitors placed at layer changes
- Breakout routing from BGA verified for impedance continuity and via optimization
- Eye diagram simulation meets mask requirements at target BER
- S-parameter analysis of channel shows insertion loss within budget
- Return loss (S11) better than −10 dB across the frequency band of interest
- Connector models included in channel simulation (S-parameter or IBIS)
- IBIS or IBIS-AMI models obtained and validated for all high-speed drivers/receivers
- Timing margins analyzed accounting for jitter, skew, and setup/hold requirements
Tip: Always verify SI simulation results with post-layout extraction. Pre-layout estimates can be optimistic — actual via transitions, BGA breakouts, and connector parasitics add loss and reflections.
Power Integrity Design Checklist
Verification items for robust power distribution network design.
Progress: 0 / 15 items
- Target impedance calculated for each power rail based on voltage tolerance and transient current
- PDN impedance simulated from DC to maximum switching frequency and verified below Ztarget
- Decoupling capacitor values selected to cover frequency range from VRM bandwidth to IC die capacitance
- Anti-resonance peaks between capacitor groups identified and mitigated
- Bulk capacitors placed near VRM output with wide copper connections
- High-frequency MLCC decoupling capacitors placed within 2 mm of IC power/ground balls
- Via inductance for decoupling capacitor mounting minimized (multiple vias per pad)
- Power/ground plane pair spacing minimized (2–4 mil core) for interplane capacitance
- IR drop analysis performed for all power planes under maximum load conditions
- Voltage regulator output capacitor and compensation network match IC datasheet recommendations
- Ferrite beads or inductors in power paths verified for self-resonance and current rating
- Current density in vias and traces verified against IPC-2152 or thermal simulation
- Power plane stitching vias placed at board edges and around plane splits
- Sense lines for voltage regulators routed correctly to point of load
- Power-up sequencing requirements verified against IC specifications and constraints
Tip: PDN design is iterative. After layout changes, re-run impedance and IR drop simulations to confirm the design still meets targets under worst-case load conditions.
EMI Pre-Compliance Checklist
Items to verify before sending the product for formal EMC compliance testing.
Progress: 0 / 15 items
- Clock signals routed on inner layers with continuous reference planes above and below
- Spread-spectrum clocking (SSC) enabled where supported by the interface standard
- All unused I/O pins configured as low-impedance outputs driven to a known state
- Cable connector areas have proper ground stitching and EMI filtering
- Common-mode chokes installed on cables that exit the enclosure (USB, Ethernet, HDMI)
- Board edge treatment: ground planes extend to board edges, no floating copper near edges
- Crystal oscillator and PLL areas shielded or isolated with guard traces and ground stitching
- High-speed signal traces do not route near board edges or connector areas
- Return current path continuity verified — no slots or splits in reference planes under signal routes
- EMI gaskets and shielding cans specified for enclosure seams and board-level shielding
- Pre-compliance scan performed with near-field probe to identify hot spots
- Conducted emissions measured on all power and signal cables with LISN
- Radiated emissions margin of at least 6 dB below applicable limits at pre-scan
- Series resistors on unused high-speed outputs to reduce slew rate and harmonic content
- All shield connections (chassis ground, cable shields) verified for low impedance at RF frequencies
Tip: Pre-compliance testing at the board level with near-field probes and a spectrum analyzer can save weeks of debugging. Identify hot spots early, before the enclosure is finalized.
Schematic Review Checklist NEW
Essential verification items for schematic completeness, correctness, and design-for-reliability before moving to layout.
Progress: 0 / 15 items
- All IC power pins connected and decoupling capacitors present
- Reset and enable pins properly terminated (not floating)
- Pull-up/pull-down resistors on open-drain/collector outputs
- Crystal load capacitor values match manufacturer recommendation
- Voltage regulator input/output capacitor values per datasheet
- ESD protection on all external-facing connectors
- Series termination resistors on clock outputs and high-speed drivers
- Net names consistent and meaningful across all sheets
- Power sequencing requirements documented and verified
- Ferrite beads rated for DC current and checked for self-resonance
- All no-connect (NC) pins explicitly marked
- Test points on all critical power rails and debug interfaces
- Proper star-point grounding for mixed-signal (analog/digital) sections
- Connector pinout verified against mating connector and cable
- Bill of materials (BOM) cross-checked against schematic
Tip: A thorough schematic review before layout starts prevents costly re-spins. Pay special attention to power sequencing — getting it wrong can damage ICs on first power-up.
Manufacturing / DFM Checklist NEW
Design for manufacturability items to review before releasing Gerber files and assembly data to the production line.
Progress: 0 / 12 items
- Minimum pad sizes meet assembly house capability
- Component orientation consistent for wave/reflow soldering
- Adequate spacing between tall components for rework access
- Solder paste stencil aperture design reviewed
- Polarity markings on PCB match component orientation
- No components under overhanging connectors or heat sinks
- Via-in-pad filled and capped where required
- Panel scoring/routing optimized for assembly yield
- Pick-and-place reference designators match centroid file
- Conformal coating keep-out areas defined
- Assembly drawings include all special instructions
- First article inspection (FAI) criteria defined
Tip: Engage your assembly house early in the design process. A 30-minute DFM review call can prevent yield issues that cost thousands in rework and delayed shipments.